System-on-Chip (SoC) technology is a driving force behind the growth and advancement of various digital technologies in our daily lives. Focussing on cyber-physical systems (CPS), the past decade has seen massive growth in demand for different kinds of SoCs, encompassing increased computational power, energy efficiency, and cost-effectiveness. To ensure the reliable functionality of SoC devices, post-silicon validation plays a pivotal role. This is one of the most intricate and costly stages of the SoC design cycle, primarily because the post-silicon validation process generates a large amount of data (e.g. trace files, electrical test reports, oscilloscope images, etc., see Figure 1). While the complexity of SoCs is growing, the amount of test data is growing too and there is pressure to reduce the post-silicon validation time amidst fierce market competition. To overcome this issue, we propose AI (artificial intelligence) for smart post-silicon validation. This is a collaborative venture between the massively parallel systems group, the smart sensors group, and NXP Hamburg.
Our project introduces an AI-powered method to automatically detect anomalies in the test traces and oscilloscope images, which provides several benefits including a reduction in validation time, errors, and accelerated time-to-market. One of the standout features of our models lies in their training on real SoC project data, thanks to NXP Hamburg for the collaboration!
Training our models on 8,044 labeled oscilloscope images—deemed 'good'—we further evaluated their performance using the Reconstruction Error (RCE) metric. Although RCE is a prevalent metric, we introduce the use of Kernel Density Estimate (KDE) to refine anomaly detection accuracy. The decision whether a given oscilloscipe image is anomalous or not is made by identifying a suitable threshold for the RCE (RCETh) and KDE (KDETh) metrics.
Figure 2 shows the model’s performance to detect anomalies in oscilloscope images. Our goal is to minimize false negatives (predicted label 0, actual label 1) to ensure that critical anomalies are not overlooked and reliable SoCs are delivered to users, while simultaneously aiming to maintain false positives (predicted label 1, actual label 0) within an acceptable range to reduce human effort. While the combination of metrics greatly reduces the number of false negatives (68%) compared to using only the RCE metric, our quest remains to drive the false negatives to zero, ensuring airtight SoC reliability.
Our journey unveils the potential for AI to revolutionize the complex and crucial process of post-silicon validation, thus bringing fast and more reliable SoCs to market to meet the growing demands of digitalization of our world by CPS.
Contact Info:
Kowshic Ahmed Akash (kowshicahmed.akash@nxp.com)
NXP Hamburg
Prof. Dr.-Ing. Sohan Lal (Tel.: +49 40 42878 2037, sohan.lal@tuhh.de)
Massively Parallel Systems Group (E-EXK5)
Prof. Dr.-Ing. Ulf Kulau (Tel.: +40 42878 2601, ulf.kulau@tuhh.de)
Smart Sensors (E-EXK3)
Hamburg University of Technology (TUHH)
Am Schwarzenberg-Campus 3, 21073 Hamburg
