Correctness is a major concern in embedded systems. Model checking can fully automatically proof formal properties about digital hardware or software. Such properties are given in temporal logic, e.g., to prove "No two orthogonal traffic lights will ever be green."
And how do the underlying reasoning algorithms work so effectively in practice despite a computational complexity of NP hardness and beyond?
But what are the limitations of model checking? How are the models generated from a given design? The lecture will answer these questions. Open source tools will be used to gather a practical experience.
Among other topics, the lecture will consider the following topics:
Modelling digital Hardware, Software, and Cyber Physical Systems
Data structures, decision procedures and proof engines
Binary Decision Diagrams
And-Inverter-Graphs
Boolean Satisfiability
Satisfiability Modulo Theories
Specification Languages
CTL
LTL
System Verilog Assertions
Algorithms for
Reachability Analysis
Symbolic CTL Checking
Bounded LTL-Model Checking
Optimizations, e.g., induction, abstraction
Quality assurance
Leistungsnachweis:
695 - Modellprüfung - Beweiser und Algorithmen<ul><li>695 - Modellprüfung - Beweiser und Algorithmen: mündlich</li></ul><br>m1397 - Modellprüfung - Beweiser und Algorithmen<ul><li>p1309 - Modellprüfung - Beweiser und Algorithmen: mündlich</li><li>vl360 - Verpflichtende Studienleistung Modellprüfung - Beweiser und Algorithmen - Fachtheoretisch-fachpraktische Studienleistung: Fachtheoretisch-fachpraktische Studienleistung</li></ul>
ECTS-Kreditpunkte:
6
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