Institute of Embedded Systems

[BibTex]

Note: doehlert, ESD

Abstract: Optical on-chip communication technology provides an unprecedented bandwidth. It allows to connect the hundreds or even thousands of processing elements expected in many core systems using optical Network-on-Chip. However, the required buffers to interface the electrical and optical layers are very large, since optical data-flow cannot be stored. Moreover, on-chip optical technologies have high defect rates which limits its usability severely. In order to address these challenges, this work presents a buffer-efficient reconfigurable optical Network-on-Chip with permanent-error recognition. The buffer-efficiency is achieved by a global credit-based arbitration with optical tokens. Further on, the architecture autonomously detects permanent errors in the optical components and configures the communication paths to avoid them. The work provides a thorough analysis at the gate-level of the area overhead incurred by the electrical sub-modules of the proposed system. It shows the practicability of the approach, experimental validated on a FPGA prototype. Compared with previously reported optical networks, it achieves an area reduction of up to 80% with almost identical performance.