Institute of Embedded Systems

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2011

  • Timon Kelter, Heiko Falk, Peter Marwedel, Sudipta Chattopadhyay and Abhik Roychoudhury (2011). Bus-Aware Multicore WCET Analysis through TDMA Offset Bounds. In Proceedings of the 23rd Euromicro Conference on Real-Time Systems (ECRTS) Porto / Portugal 3-12 [Abstract] [BibTex]

  • Timon Kelter, Heiko Falk, Peter Marwedel, Sudipta Chattopadhyay and Abhik Roychoudhury (2011). Bus-Aware Multicore WCET Analysis through TDMA Offset Bounds. Dortmund / Germany [Abstract] [BibTex]

  • Stefan Frehse and Finn Haedicke and Melanie Diepenbeck and Goerschwin Fey and Rolf Drechsler (2011). Hochoptimierter Ablauf zur Robustheitsprüfung. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) 35-42 [BibTex]

2010

  • Mehwish Saleemi and Karl-Heinz Zimmermann (2010). From ideals in polynomial rings to linear codes using Groebner bases. International Journal of Pure and Applied Mathematics (IJPAM). 65. (1), 41-54 [Abstract] [BibTex]

  • Cem Savas Bassoy, Svetlana Torgasin, Mei Yang and Karl-Heinz Zimmermann (2010). Accelerating Scalar-Product Based Sequence Alignment using Graphics Processor Units. Journal of Signal Processing Systems. 61. (2), 117-125 [Abstract] [BibTex]

  • Heiko Falk and Paul Lokuciejewski (2010). A compiler framework for the reduction of worst-case execution times. the International Journal of Time-Critical Computing Systems (Real-Time Systems). 46. (2), 251-300 [Abstract] [BibTex]

  • Mehwish Saleemi and Karl-Heinz Zimmermann (2010). Groebner bases for linear codes. International Journal of Pure and Applied Mathematics (IJPAM). 62. (4), 481-491 [Abstract] [BibTex]

  • Oscar Mauricio Reyes and Karl-Heinz Zimmermann (2010). Permutation parity machines for neural cryptography. Physical Review E. 81. (6), [Abstract] [BibTex]

  • Mehwish Saleemi and Karl-Heinz Zimmermann (2010). Linear codes as binomial ideals. International Journal of Pure and Applied Mathematics (IJPAM). 61. (2), 147-156 [Abstract] [BibTex]

  • Paul Lokuciejewski, Sascha Plazar, Heiko Falk, Peter Marwedel and Lothar Thiele (2010). Multi-Objective Exploration of Compiler Optimizations for Real-Time Systems. In Proceedings of the 13th International Symposium on Object/Component/Service-oriented Real-time Distributed Computing (ISORC) Carmona / Spain 115-122 [Abstract] [BibTex]

  • Peter Marwedel and Heiko Falk (2010). Reconciling compilers and timing analysis. Stockholm / Sweden [BibTex]

  • Wolfgang Kramper (2010). Simulation von Schwarmverhalten. Mensch & Buch: [BibTex]

  • Israel Marck Martinez-Perez, Wolfgang Brandt, Michael Wild and Karl-Heinz Zimmermann (2010). Bioinspired Parallel Algorithms for Maximum Clique Problem on FPGA Architectures. Journal of Signal Processing Systems. 58. (2), 117-124 [Abstract] [BibTex]

  • Mehwish Saleemi and Karl-Heinz Zimmermann (2010). Groebner bases for a class of ideals in commutative polynomial rings. International Journal of Pure and Applied Mathematics (IJPAM). 58. (1), 1-9 [Abstract] [BibTex]

  • Svetlana Torgasin and Karl-Heinz Zimmermann (2010). Algorithm for thermodynamically based prediction of DNA/DNA crosshybridization. International Journal of Bioinformatics Research and Applications (IJBRA). 6. (1), 82-97 [Abstract] [BibTex]

  • Karl-Heinz Zimmermann (2010). Und, wie hoch ist Ihre Erdös-Zahl?. Spektrum Magazin. [BibTex]

  • Rolf Drechsler and Goerschwin Fey (2010). Formal verification meets robustness checking - techniques and challenges (Tutorial). [BibTex]

  • Stephan Eggersglüß and Goerschwin Fey and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel and Rolf Drechsler (2010). MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. Journal of Electronic Testing: Theory and Applications (JETTA). 307-322 [BibTex]

  • Stefan Frehse and Goerschwin Fey (2010). Kompositionelle Formale Robustheitsprüfung. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) 73-74 [BibTex]

  • Alexander Finder and Goerschwin Fey (2010). Evaluating Debugging Algorithms from a Qualitative Perspective. Forum on Specification and Design Languages (FDL) [BibTex]

  • Alexander Finder and Goerschwin Fey (2010). Evaluating Debugging Algorithms from a Qualitative Perspective. Int'l Workshop on Boolean Problems (IWSBP) [BibTex]

  • Stefan Frehse and Goerschwin Fey and Rolf Drechsler (2010). A Better-Than-Worst-Case Robustness Measure. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) 78-83 [BibTex]

  • Stefan Frehse and Goerschwin Fey and Rolf Drechsler (2010). A Better-Than-Worst-Case Robustness Measure. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ) 19-24 [BibTex]

  • Stefan Frehse and Goerschwin Fey and Rolf Drechsler (2010). A Better-Than-Worst-Case Robustness Measure. Int'l Test Conference (ITC) [BibTex]

  • Stefan Frehse and Goerschwin Fey and André Sülflow and Rolf Drechsler (2010). RobuCheck: A Robustness Checker for Digital Circuits. EUROMICRO Symposium on Digital System Design (DSD) 226-231 [BibTex]

  • Stefan Frehse and Goerschwin Fey and André Sülflow and Rolf Drechsler (2010). RobuCheck: A Robustness Checker for Digital Circuits. Workshop on Dynamic Aspects in Dependability Model for Fault-Tolerant Systems (DYADEM-FTS) 37-38 [BibTex]

  • Goerschwin Fey and André Sülflow and Rolf Drechsler (2010). Towards Unifying Localization and Explanation for Automated Debugging. International Workshop on Microprocessor Test and Verification (MTV) 3-8 [BibTex]

  • Goerschwin Fey and André Sülflow and Stefan Frehse and Rolf Drechsler (2010). Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen. it - Information Technology. 216-222 [BibTex]

  • Goerschwin Fey (Organizer) (2010). Design Closure for Reliability. [BibTex]

  • Finn Haedicke and Bijan Alizadeh and Goerschwin Fey and Masahiro Fujita and Rolf Drechsler (2010). Polynomial Datapath Optimization using Constraint Solving and Formal Modelling. IEEE/ACM Int'l Conf. on CAD (ICCAD) 756-761 [BibTex]

  • André Sülflow and Goerschwin Fey and Rolf Drechsler (2010). Using QBF to Increase Accuracy of SAT-Based Debugging. IEEE Int'l Symposium on Circuits and Systems (ISCAS) 641-644 [BibTex]

  • André Sülflow and Goerschwin Fey and Rolf Drechsler (2010). Bounded Fault Tolerance Checking (Invited Talk). Forum on Specification and Design Languages (FDL) [BibTex]

2009

  • Oscar Mauricio Reyes Torres and Karl-Heinz Zimmermann (2009). Key exchange protocol using permutation parity machines. In Proceedings of the International Joint Conference on Computational Intelligence (IJCCI) Madeira / Portugal 496-501 [BibTex]

  • Heiko Falk and Jan C. Kleinsorge (2009). Optimal Static WCET-aware Scratchpad Allocation of Program Code. In Proceedings of the 46th Design Automation Conference (DAC) San Francisco / USA 732-737 [Abstract] [BibTex]

  • Heiko Falk (2009). WCET-aware Register Allocation based on Graph Coloring. In Proceedings of the 46th Design Automation Conference (DAC) San Francisco / USA 726-731 [Abstract] [BibTex]

  • Heiko Falk (Ed.) (2009). Proceedings of the 12th International Workshop on Software & Compilers for Embedded Systems (SCOPES). ACM: Nice / France [www] [BibTex]

  • Heiko Falk (2009). Compiler Techniques for hard Real-Time Systems (in German). Schloss Dagstuhl / Germany [BibTex]

  • Oscar Mauricio Reyes Torres, I. Kopitzke and Karl-Heinz Zimmermann (2009). Permutation parity machines for neural synchronization. Journal of Physics A: Mathematical and Theoretical. 42. (19), [Abstract] [BibTex]

  • Paul Lokuciejewski, Daniel Cordes, Heiko Falk and Peter Marwedel (2009). A Fast and Precise Static Loop Analysis based on Abstract Interpretation, Program Slicing and Polytope Models. In Proceedings of the International Symposium on Code Generation and Optimization (CGO) Seattle / USA 136-146 [Abstract] [BibTex]

  • Israel Marck Martinez-Perez and Karl-Heinz Zimmermann (2009). Parallel bioinspired algorithms for NP complete graph problems. Journal of Parallel and Distributed Computing (JPDC). 69. (3), 221-229 [Abstract] [BibTex]

  • Israel Marck Martinez-Perez, Karl-Heinz Zimmermann and Zoya Ignatova (2009). An autonomous DNA model for finite state automata. International Journal of Bioinformatics Research and Applications (IJBRA). 5. (1), 81-96 [Abstract] [BibTex]

  • Israel Marck Martinez-Perez, Zoya Ignatova and Karl-Heinz Zimmermann (2009). Exploiting the Features of the Finite State Automata for Biomolecular Computing. Journal on Recent Patents on DNA & Gene Sequences. 3. (2), 130-138 [Abstract] [BibTex]

  • Dominique Borrione and Rolf Drechsler and Emmanuelle Encrenaz-Tiphene and Goerschwin Fey (2009). Formal and Semi-formal Methods for Correctness and Robustness (Tutorial). [BibTex]

  • Rolf Drechsler and Stephan Eggersglüß and Goerschwin Fey and Daniel Tille (2009). Test Pattern Generation using Boolean Proof Engines. [BibTex]

  • Rolf Drechsler and Stephan Eggersglüß and Goerschwin Fey and Daniel Tille (2009). Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern. it - Information Technology. 102-111 [BibTex]

  • Rolf Drechsler and Stephan Eggersglüß and Goerschwin Fey and Daniel Tille (2009). SAT-based Automatic Test Pattern Generation. Evolutionary Test Generation Dagstuhl-Seminar [BibTex]

  • Rolf Drechsler and Goerschwin Fey (2009). Formale Verifikation und Robustheit (Tutorial). [BibTex]

  • Stefan Frehse and Goerschwin Fey and André Sülflow and Rolf Drechsler (2009). Robustness Check for Multiple Faults using Formal Techniques. EUROMICRO Symposium on Digital System Design (DSD) 85-90 [BibTex]

  • Stefan Frehse and Goerschwin Fey and André Sülflow and Rolf Drechsler (2009). Robustness Check for Multiple Faults using Formal Techniques. Workshop on Constraints in Formal Verification (CFV) [BibTex]

  • Goerschwin Fey and André Sülflow and Rolf Drechsler (2009). Computing Bounds for Fault Tolerance using Formal Techniques. Design Automation Conference (DAC) 190-195 [BibTex]

  • Goerschwin Fey (2009). Deterministic Algorithms for ATPG under Leakage Constraints. Asian Test Symposium (ATS) 313-316 [BibTex]

  • Goerschwin Fey (2009). Algorithms for ATPG under Leakage Constraints. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ) 91-96 [BibTex]

  • Toru Nakura and Yutaro Tatemura and Goerschwin Fey and Makoto Ikeda and Satoshi Komatsu and Kunihiro Asada (2009). SAT-Based ATPG Testing of Inter- and Intra-Gate Bridging Faults. European Conference on Circuit Theory and Design (ECCTD) 643-647 [BibTex]

  • Frank Rogin and Thomas Klotz and Goerschwin Fey and Rolf Drechsler and Steffen Rülke (2009). Advanced Verification by Automatic Property Generation. IET Computers and Digital Techniques. 338-353 [BibTex]

  • André Sülflow and Goerschwin Fey and Cecile Braunstein and Ulrich Kühne and Rolf Drechsler (2009). Increasing the Accuracy of SAT-based Debugging. Design, Automation and Test in Europe (DATE) 1326-1331 [BibTex]

  • André Sülflow and Goerschwin Fey and Cecile Braunstein and Ulrich Kühne and Rolf Drechsler (2009). Increasing the Accuracy of SAT-based Debugging. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) [BibTex]

  • André Sülflow and Goerschwin Fey and Rolf Drechsler (2009). Using QBF to Increase Accuracy of SAT-based Debugging. Workshop on Constraints in Formal Verification (CFV) [BibTex]

  • André Sülflow and Stefan Frehse and Goerschwin Fey and Rolf Drechsler (2009). Anwendungsbezogene Analyse der Robustheit von digitalen Schaltungen. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) 45-52 [BibTex]

  • André Sülflow and Ulrich Kühne and Goerschwin Fey and Daniel Große and Rolf Drechsler (2009). WoLFram - A Word Level Framework for Formal Verification. IEEE/IFIP Int'l Symposium on Rapid System Prototyping (RSP) 11-17 [BibTex]

  • André Sülflow and Robert Wille and Goerschwin Fey and Rolf Drechsler (2009). Evaluation of Cardinality Constraints on SMT-based Debugging. IEEE Int'l Symposium on Multi-Valued Logic (ISMVL) 298-303 [BibTex]

  • Robert Wille and Goerschwin Fey and Daniel Große and Stephan Eggersglüß and Rolf Drechsler (2009). SWORD: A SAT like prover using word level information. VLSI-SoC: Advanced Topics on Systems on a Chip 175-192 [BibTex]

2008

  • Heiko Falk (2008). Memory-architecture aware compilation. Dresden / Germany [BibTex]

  • Peter Marwedel and Heiko Falk (2008). Memory-architecture aware compilation. Autrans / France [www] [BibTex]

  • Peter Marwedel and Heiko Falk (2008). Embedded Systems - with Emphasis on the Exploitation of the Memory Hierarchy. Seoul / South Korea [BibTex]

  • Zoya Ignatova, Israel Marck Martinez-Perez and Karl-Heinz Zimmermann (2008). DNA Computing Models. Springer: [Abstract] [BibTex]

  • Paul Lokuciejewski, Heiko Falk and Peter Marwedel (2008). WCET-driven Cache-based Procedure Positioning Optimizations. In Proceedings of the 20th Euromicro Conference on Real-Time Systems (ECRTS) Prague / Czech Republic 321-330 [Abstract] [BibTex]

  • Heiko Falk (Ed.) (2008). Proceedings of the 11th International Workshop on Software & Compilers for Embedded Systems (SCOPES). ACM: Munich / Germany [www] [BibTex]

  • Paul Lokuciejewski, Heiko Falk, Peter Marwedel and Henrik Theiling (2008). WCET-Driven, Code-Size Critical Procedure Cloning. In Proceedings of the 11th International Workshop on Software & Compilers for Embedded Systems (SCOPES) Munich / Germany 21-30 [Abstract] [BibTex]

  • Rolf Drechsler and Stephan Eggersglüß and Goerschwin Fey and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel and Daniel Tille (2008). On Acceleration of SAT-based ATPG for Industrial Designs. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 1329-1333 [BibTex]

  • Goerschwin Fey and Anna Bernasconi and Valentina Ciriani and Rolf Drechsler (2008). On the Construction of Small Fully Testable Circuits with Low Depth. Microprocessors and Microsystems (MICPRO). 263-269 [BibTex]

  • Goerschwin Fey and Rolf Drechsler (2008). A Basis for Formal Robustness Checking. Int'l Symposium on Quality Electronic Design (ISQED) 784-789 [BibTex]

  • Goerschwin Fey and Rolf Drechsler (2008). Robustness and Usability in Modern Design Flows. [BibTex]

  • Goerschwin Fey and Rolf Drechsler (2008). Synthesis for Detection of Transient Faults. IEICE Workshop on Dependable Computing 161-166 [BibTex]

  • Goerschwin Fey and Satoshi Komatsu and Yasuo Furukawa and Masahiro Fujita (2008). Targeting Leakage Constraints during ATPG. Asian Test Symposium (ATS) 225-230 [BibTex]

  • Goerschwin Fey and Satoshi Komatsu and Yasuo Furukawa and Masahiro Fujita (2008). Targeting Leakage Constraints during ATPG. IEEE Int'l Workshop on Silicon Debug and Diagnosis (SDD) [BibTex]

  • Goerschwin Fey and Stefan Staber and Roderick Bloem and Rolf Drechsler (2008). Automatic Fault Localization for Property Checking. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 1138-1149 [BibTex]

  • Goerschwin Fey and Stefan Staber and Roderick Bloem and Rolf Drechsler (2008). Automatic Fault Localization for Property Checking. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 1138-1149 [BibTex]

  • Goerschwin Fey and André Sülflow and Stefan Frehse and Ulrich Kühne and Rolf Drechsler (2008). Formaler Nachweis der Fehlertoleranz von Schaltkreisen. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) 75-82 [BibTex]

  • Frank Rogin and Thomas Klotz and Goerschwin Fey and Rolf Drechsler and Steffen Rülke (2008). Automatic Generation of Complex Properties for Hardware Designs. Design, Automation and Test in Europe (DATE) 545-548 [BibTex]

  • Frank Rogin and Thomas Klotz and Steffen Rülke and Goerschwin Fey and Rolf Drechsler (2008). Effiziente automatische Generierung von Assertions für industrielle Hardware-Designs. Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS) [BibTex]

  • André Sülflow and Goerschwin Fey and Roderick Bloem and Rolf Drechsler (2008). Using Unsatisfiable Cores to Debug Multiple Design Errors. Great Lakes Symp. VLSI (GLS) 77-82 [BibTex]

  • André Sülflow and Goerschwin Fey and Roderick Bloem and Rolf Drechsler (2008). Debugging Design Errors by Using Unsatisfiable Cores. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 159-168 [doi] [BibTex]

  • André Sülflow and Goerschwin Fey and Rolf Drechsler (2008). Experimental Studies on SMT-based Debugging. IEEE Workshop on RTL and High Level Testing (WRTLT) 93-98 [BibTex]

  • André Sülflow and Goerschwin Fey and Stefan Frehse and Ulrich Kühne and Rolf Drechsler (2008). Computing Bounds for Fault Tolerance using Formal Techniques. Workshop on Design for Reliability and Variability (DRV) [BibTex]

  • Robert Wille and Goerschwin Fey and Marc Messing and Gerhard Angst and Lothar Linhard and Rolf Drechsler (2008). Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. EUROMICRO Symposium on Digital System Design (DSD) 542-549 [BibTex]

2007

  • Israel Marck Martinez-Perez (2007). Biomolecular Computing Models for Graph Problems and Finite State Automata. Hamburg / Germany [BibTex]

  • Heiko Falk, Sascha Plazar and Henrik Theiling (2007). Compile-Time Decided Instruction Cache Locking Using Worst-Case Execution Paths. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Salzburg / Austria 143-148 [Abstract] [BibTex]

  • Israel Marck Martinez-Perez, Zoya Ignatova and Karl-Heinz Zimmermann (2007). Computational genes: a tool for molecular diagnosis and therapy of aberrant mutational phenotype. BMC Bioinformatics. 8. (365), [BibTex]

  • Heiko Falk and Peter Marwedel (Eds.) (2007). Proceedings of the 10th International Workshop on Software & Compilers for Embedded Systems (SCOPES). ACM: Nice / France [www] [BibTex]

  • Björn Saballus, Markus Volkmer and Sebastian Wallner (2007). Secure Group Communication in Ad-Hoc Networks using Tree Parity Machines. In Proceedings of the 4th Workshop on Mobile Ad-Hoc Networks (WMAN) Bern / Switzerland [Abstract] [BibTex]

  • Goerschwin Fey and Anna Bernasconi and Valentina Ciriani and Rolf Drechsler (2007). On the Construction of Small Fully Testable Circuits with Low Depth. EUROMICRO Symposium on Digital System Design (DSD) 563-569 [BibTex]

  • Goerschwin Fey and Rolf Drechsler (2007). Ein formaler Ansatz zum Robustheitsnachweis. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) 101-108 [BibTex]

  • Goerschwin Fey and Rolf Drechsler (2007). Formal Robustness Checking. Workshop on Constraints in Formal Verification (CFV) [BibTex]

  • Goerschwin Fey and Daniel Große and Stephan Eggersglüß and Robert Wille and Rolf Drechsler (2007). Formal Verification on the Word Level using SAT-like Proof Techniques. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) [BibTex]

  • Goerschwin Fey and Tim Warode and Rolf Drechsler (2007). Using Structural Learning Techniques in SAT-based ATPG. VLSI Design Conference 69-74 [BibTex]

  • Goerschwin Fey (2007). Increasing Robustness and Usability of Circuit Design Tools by Using Formal Techniques. Ausgezeichnete Informatikdissertationen 2006 29-38 [BibTex]

  • Daniel Große and Goerschwin Fey and Rolf Drechsler (editors) (2007). SATRIX - Algorithmen für Boolesche Erfüllbarkeit. [BibTex]

  • André Sülflow and Goerschwin Fey and Rolf Drechsler (2007). Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) [BibTex]

  • Daniel Tille and Stephan Eggersglüß and Görschwin Fey and Rolf Drechsler and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel (2007). Studies on Integrating SAT-based ATPG in an Industrial Environment. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ) [BibTex]

  • Daniel Tille and Goerschwin Fey and Rolf Drechsler (2007). Instance Generation for SAT-based ATPG. IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS) [BibTex]

Eintrag 301-400 von 544
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