Institute of Embedded Systems

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2007

  • Peter Marwedel, Heiko Falk, Sascha Plazar, Robert Pyka and Lars Wehmeyer (2007). Automatic mapping to tightly-coupled memories and cache locking. Cambridge / UK [BibTex]

  • Paul Lokuciejewski, Heiko Falk, Martin Schwarzer, Peter Marwedel and Henrik Theiling (2007). Influence of Procedure Cloning on WCET Prediction. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Salzburg / Austria 137-142 [Abstract] [BibTex]

  • Karl-Heinz Zimmermann, Zoya Ignatova and Israel Marck Martinez-Perez (2007). Rechengen. Munich / Germany [www] [BibTex]

  • Paul Lokuciejewski, Heiko Falk, Martin Schwarzer and Peter Marwedel (2007). Tighter WCET Estimates by Procedure Cloning. In Proceedings of the 7th International Workshop on Worst-Case Execution Time Analysis (WCET) Pisa / Italy 27-32 [Abstract] [BibTex]

  • Robert Pyka, Christoph Faßbach, Manish Verma, Heiko Falk and Peter Marwedel (2007). Operating system integrated energy aware scratchpad allocation strategies for multiprocess applications. In Proceedings ot the 10th International Workshop on Software & Compilers for Embedded Systems (SCOPES) Nice / France 41-50 [Abstract] [BibTex]

  • Rolf Drechsler and Goerschwin Fey and Sebastian Kinder (2007). An Integrated Approach for Combining BDDs and SAT Provers. Facta Universitatis. 415-436 [BibTex]

  • Stephan Eggersglüß and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel (2007). Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. ACM/IEEE Int'l Conference on Formal Methods and Models for Codesign (MEMOCODE) 181-187 [BibTex]

  • Stephan Eggersglüß and Goerschwin Fey and Rolf Drechsler (2007). SAT-based ATPG for Path Delay Faults in Sequential Circuits. IEEE Int'l Symposium on Circuits and Systems (ISCAS) 3671-3674 [BibTex]

  • Sebastian Kinder and Goerschwin Fey and Rolf Drechsler (2007). Estimating the Quality of AND-EXOR Optimization Results. Int'l Workshop on Applications of the Reed-Muller Expansion in Circuit Design [BibTex]

  • Stephan Eggersglüß and Daniel Tille and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel (2007). Experimental Studies on SAT-based ATPG for Gate Delay Faults. IEEE Int'l Symposium on Multi-Valued Logic (ISMVL) 6 (6 pages) [BibTex]

  • Robert Wille and Goerschwin Fey and Rolf Drechsler (2007). Building Free Binary Decision Diagrams Using SAT Solvers. Int'l Workshop on Applications of the Reed-Muller Expansion in Circuit Design [BibTex]

  • Robert Wille and Goerschwin Fey and Rolf Drechsler (2007). Building Free Binary Decision Diagrams Using SAT Solvers. Facta Universitatis. 381-394 [BibTex]

  • Robert Wille and Goerschwin Fey and Daniel Große and Stephan Eggersglüß and Rolf Drechsler (2007). SWORD: A SAT like prover using word level information. IEEE/IFIP Int'l Conference on VLSI and System-on-Chip (VLSI-SoC) 88-93 [BibTex]

2006

  • Israel Marck Martinez-Perez, Zhang Gong, Zoya Ignatova and Karl-Heinz Zimmermann (2006). Solving the Maximum Clique Problem via DNA Hairpin Formation. Hamburg / Germany [BibTex]

  • Heiko Falk, Jens Wagner and André Schaefer (2006). Use of a Bit-true Data Flow Analysis for Processor-Specific Source Code Optimization. In Proceedings of the 4th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia) Seoul / South Korea 133-138 [Abstract] [BibTex]

  • Heiko Falk, Paul Lokuciejewski and Henrik Theiling (2006). Design of a WCET-Aware C Compiler. In Proceedings of the 4th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia) Seoul / South Korea 121-126 [Abstract] [BibTex]

  • Heiko Falk and Martin Schwarzer (2006). Loop Nest Splitting for WCET-Optimization and Predictability Improvement. In Proceedings of the 4th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia) Seoul / South Korea 115-120 [Abstract] [BibTex]

  • Karl Tyss (2006). Generatoren für echte Zufallszahlen auf FPGAs für eingebettete Systeme. In Proceedings of Workshop über Kryptographie (5. Krypto-Tag) Kassel / Germany 4 [BibTex]

  • Karl-Heinz Zimmermann (2006). Diskrete Mathematik. Books on Demand: [BibTex]

  • Heiko Falk, Paul Lokuciejewski and Henrik Theiling (2006). Design of a WCET-Aware C Compiler. In Proceedings of the 6th International Workshop on Worst-Case Execution Time Analysis (WCET) Dresden / Germany [Abstract] [BibTex]

  • Heiko Falk and Martin Schwarzer (2006). Loop Nest Splitting for WCET-Optimization and Predictability Improvement. In Proceedings of the 6th International Workshop on Worst-Case Execution Time Analysis (WCET) Dresden / Germany [Abstract] [BibTex]

  • Andreas Ruttor and Markus Volkmer (2006). Theorie und Anwendungen von Tree Parity Machines für die Kryptographie. In Proceedings of Workshop über Kryptographie (Kryptowochenende 2006) Mannheim / Germany 20-22 [BibTex]

  • Peter Marwedel and Heiko Falk (2006). Memory- and timing-aware compilation. Düsseldorf / Germany [BibTex]

  • Israel Marck Martinez-Perez, Zoya Ignatova and Karl-Heinz Zimmermann (2006). An Autonomous DNA Model for Stochastic Finite State Automata. Hamburg / Germany [BibTex]

  • Israel Marck Martinez-Perez, Zoya Ignatova and Karl-Heinz Zimmermann (2006). An Autonomous DNA Model for Finite State Automata. Hamburg / Germany [BibTex]

  • Sascha Mühlbach, Markus Volkmer and Sebastian Wallner (2006). Encrypted and Authenticated Communication via Tree-Parity Machines in AMBA Bus Systems. In Proceedings of Workshop über Kryptographie (4. Krypto-Tag) Bochum / Germany 10 [BibTex]

  • Markus Volkmer (2006). On proving Completeness, Soundness and Security of Authenticated Tree Parity Machine Key Exchange. In Proceedings of Workshop über Kryptographie (4. Krypto-Tag) Bochum / Germany 5 [BibTex]

  • Markus Volkmer (2006). Entity Authentication and Authenticated Key Exchange with Tree Parity Machines. IACR: [Abstract] [BibTex]

  • Markus Volkmer and Sebastian Wallner (2006). Ein IP-Core Design für Schlüsselaustausch, Stromchiffre und Identifikation auf ressourcenbeschränkten Geräten. In Proceedings of Sicherheit - Schutz und Zuverlässigkeit (SICHERHEIT 2006) Magdeburg / Germany 294-297 [Abstract] [BibTex]

  • Rolf Drechsler and Goerschwin Fey (2006). Automatic Test Pattern Generation. School on Formal Methods for Hardware Verification 30-55 [BibTex]

  • Rolf Drechsler and Goerschwin Fey and Sebastian Kinder (2006). An Integrated Approach for Combining BDD and SAT Provers. VLSI Design Conference 237-242 [BibTex]

  • Goerschwin Fey and Rolf Drechsler (2006). SAT-based Calculation of Source Code Coverage for BMC. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 163-170 [BibTex]

  • Goerschwin Fey and Rolf Drechsler (2006). Minimizing the Number of Paths in BDDs - Theory and Algorithm. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 4-11 [BibTex]

  • Goerschwin Fey and Daniel Große and Rolf Drechsler (2006). Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks. Design, Automation and Test in Europe (DATE) 1225-1226 [BibTex]

  • Goerschwin Fey and Junhao Shi and Rolf Drechsler (2006). Efficiency of multiple-valued encoding in SAT-based ATPG. IEEE Int'l Symposium on Multi-Valued Logic (ISMVL) 25 (6 pages) [BibTex]

  • Goerschwin Fey and Junhao Shi and Rolf Drechsler (2006). Efficiency of multiple-valued encoding in SAT-based ATPG. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ) 107-108 [BibTex]

  • Goerschwin Fey and Sean Safarpour and Andreas Veneris and Rolf Drechsler (2006). On the Relation Between Simulation-based and SAT-based Diagnosis. Design, Automation and Test in Europe (DATE) 1139-1144 [BibTex]

  • Goerschwin Fey and Tim Warode and Rolf Drechsler (2006). Using Structural Learning Techniques in SAT-based ATPG. Int'l Workshop on Boolean Problems (IWSBP) 63-69 [BibTex]

  • Goerschwin Fey (2006). Increasing Robustness and Usability of Circuit Design Tools by Using Formal Techniques. [BibTex]

  • Stefan Staber and Goerschwin Fey and Roderick Bloem and Rolf Drechsler (2006). Automatic Fault Localization for Property Checking. IBM Haifa Verification Conference (HVC) 50-64 [BibTex]

2005

  • Manish Verma, Klaus Petzold, Lars Wehmeyer, Heiko Falk and Peter Marwedel (2005). Scratchpad Sharing Strategies for Multiprocess Embedded Systems: A First Approach. In Proceedings of the 3rd IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia) Jersey City / United States 115-120 [Abstract] [BibTex]

  • Markus Volkmer and Florian Grewe (2005). Runners, Starting Lines and Mutual Distances: On the Security of Tree Parity Machine Key Exchange. In Proceedings of Workshop über Kryptographie (3. Krypto-Tag) Darmstadt / Germany 5 [BibTex]

  • Markus Volkmer and Sebastian Wallner (2005). A Key Establishment IP-Core for Ubiquitous Computing. In Proceedings of 16th International Workshop on Database and Expert Systems Applications Copenhagen / Denmark 241-245 [Abstract] [BibTex]

  • Markus Volkmer and Sebastian Wallner (2005). Tree Parity Machine Rekeying Architectures for Embedded Security. IACR: [Abstract] [BibTex]

  • Markus Volkmer and Sebastian Wallner (2005). Lightweight Key Exchange and Stream Cipher based solely on Tree Parity Machines. In Proceedings of the ECRYPT Workshop on RFID and Lightweight Crypto Graz / Austria [Abstract] [BibTex]

  • Markus Volkmer and Sebastian Wallner (2005). Tree parity machine rekeying architectures. IEEE Transactions on Computers. 54. (4), 421-427 [Abstract] [BibTex]

  • Heiko Falk (2005). Control Flow driven Code Hoisting at the Source Code Level. In Proceedings of the 3rd Workshop on Optimizations for DSP and Embedded Systems (ODES) San Jose / United States [Abstract] [BibTex]

  • Kolja Elssel and Karl-Heinz Zimmermann (2005). Two New Nonlinear Binary Codes. IEEE Transactions on Information Theory. 51. (3), 1189-1190 [Abstract] [BibTex]

  • Björn Saballus (2005). Secure Group Communication in WLAN Ad-Hoc Networks with Tree Parity Machines. In Proceedings of Workshop über Kryptographie (2. Krypto-Tag) Ulm / Germany 12 [BibTex]

  • Nazita Behroozi (2005). Immediate Rekeying by Tree Parity Machines in a WLAN-System. In Proceedings of Workshop über Kryptographie (2. Krypto-Tag) Ulm / Germany 10 [BibTex]

  • Karl-Heinz Zimmermann (2005). Solving constrained combinatorial optimization problems via importance sampling in the grand canonical ensemble. Computer Physics Communications. 165. (3), 243-259 [Abstract] [BibTex]

  • Israel Marck Martinez-Perez, Zhang Gong, Zoya Ignatova and Karl-Heinz Zimmermann (2005). Biomolecular autonomous solution of the Hamiltonian path problem via hairpin formation. International Journal of Bioinformatics Research and Applications (IJBRA). 1. (4), 389-398 [Abstract] [BibTex]

  • Andreas Breiter and Goerschwin Fey and Rolf Drechsler (2005). Project-Based Learning in Student Teams in Computer Science Education. Facta Universitatis. 165-180 [BibTex]

  • Rolf Drechsler and Goerschwin Fey and Christian Genz and Daniel Große (2005). SyCE: An Integrated Environment for System Design in SystemC. IEEE Int'l Workshop on Rapid System Prototyping (RSP) 258-260 [BibTex]

  • Rüdiger Ebendt and Goerschwin Fey and Rolf Drechsler (2005). Advanced BDD Optimization. [BibTex]

  • Goerschwin Fey and Rolf Drechsler (2005). Efficient Hierarchical System Debugging for Property Checking. IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS) 41-46 [BibTex]

  • Goerschwin Fey and Rolf Drechsler (editors) (2005). FunTaskIC - Eine integrierte Entwurfsumgebung für SystemC. [BibTex]

  • Sebastian Kinder and Goerschwin Fey and Rolf Drechsler (2005). Controlling the Memory During Manipulation of Word-Level Decision Diagrams. IEEE Int'l Symposium on Multi-Valued Logic (ISMVL) 250-255 [BibTex]

  • Junhao Shi and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Juergen Schloeffel and Friedrich Hapke (2005). PASSAT: Efficient SAT-based Test Pattern Generation. IEEE Annual Symposium on VLSI (ISVLSI) 212-217 [BibTex]

  • Junhao Shi and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Juergen Schloeffel and Friedrich Hapke (2005). Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits. IEEE Int'l Conference on ASIC (ASICON) [BibTex]

  • Junhao Shi and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Juergen Schloeffel and Friedrich Hapke (2005). PASSAT: Efficient SAT-based Test Pattern Generation. IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS) 166-173 [BibTex]

  • Junhao Shi and Goerschwin Fey and Rolf Drechsler (2005). Bridging Fault Testability of BDD Circuits. ASP Design Automation Conference (ASPDAC) 188-191 [BibTex]

  • Sean Safarpour and Goerschwin Fey and Andreas Veneris and Rolf Drechsler (2005). Utilizing Don't Care States in SAT-based Bounded Sequential Problems. Great Lakes Symp. VLSI (GLS) 264-269 [BibTex]

2004

  • André Schaumburg (2004). Authentication within Tree Parity Machine Rekeying. In Proceedings of Workshop über Kryptographie (1. Krypto-Tag) Mannheim / Germany 13 [BibTex]

  • Heiko Falk and Peter Marwedel (2004). Source Code Optimization Techniques for Data Flow Dominated Embedded Software. Kluwer Academic Publishers: [Abstract] [BibTex]

  • Markus Volkmer and Sebastian Wallner (2004). A Low-Cost Solution for Frequent Symmetric Key Exchange in Ad-hoc Networks. In Proceedings of the Workshop Mobile Ad-hoc Netzwerke (WMAN) Ulm / Germany 128-132 [Abstract] [BibTex]

  • Heiko Falk and Manish Verma (2004). Combined Data Partitioning and Loop Nest Splitting for Energy Consumption Minimization. In Proceedings of the 8th International Workshop on Software & Compilers for Embedded Systems (SCOPES) Amsterdam / The Netherlands 137-151 [Abstract] [BibTex]

  • Heiko Falk (2004). Source Code Optimization Techniques for Data Flow Dominated Embedded Software. Dortmund / Germany [Abstract] [BibTex]

  • Wolfgang Achtziger, Andreas Popp and Karl-Heinz Zimmermann (2004). Optimization and Parallelization of Loop Nests via Linear Vector-Valued Schedules. Dortmund / Germany [Abstract] [BibTex]

  • Nicole Drechsler and Mario Hilgemeier and Goerschwin Fey and Rolf Drechsler (2004). Disjoint Sum of Product Minimization by Evolutionary Algorithms. Applications of Evolutionary Computing: EvoWorkshops 198-207 [BibTex]

  • Rolf Drechsler and Junhao Shi and Goerschwin Fey (2004). Synthesis of Fully Testable Circuits from BDDs. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 440-443 [BibTex]

  • Goerschwin Fey and Rolf Drechsler (2004). Improving Simulation-Based Verification by Means of Formal Methods. ASP Design Automation Conference (ASPDAC) 640-643 [BibTex]

  • Goerschwin Fey and Rolf Drechsler (2004). Visualization of Diagnosis Results for Design Debugging. Internatinal Workshop on Post-Binary ULSI Systems (ULSIWS) 1-2 [BibTex]

  • Rolf Drechsler and Goerschwin Fey (2004). Design Understanding by Automatic Property Generation. Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 274-281 [BibTex]

  • Goerschwin Fey and Rolf Drechsler and Maciej Ciesielski (2004). Algorithms for Taylor Expansion Diagrams. IEEE Int'l Symposium on Multi-Valued Logic (ISMVL) 235-240 [BibTex]

  • Goerschwin Fey and Daniel Große and Tim Cassens and Christian Genz and Tim Warode and Rolf Drechsler (2004). ParSyC: An Efficient SystemC Parser. Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 148-154 [BibTex]

  • Goerschwin Fey and Junhao Shi and Rolf Drechsler (2004). BDD Circuit Optimization for Path Delay Fault Testability. EUROMICRO Symposium on Digital System Design (DSD) 162-172 [BibTex]

  • Klaus Winkelmann and Hans-Joachim Trylus and Dominik Stoffel and Goerschwin Fey (2004). Cost-efficient Block Verification for a UMTS Up-link Chip-rate Coprocessor. Design, Automation and Test in Europe (DATE) 162-167 [BibTex]

2003

  • Heiko Falk (2003). Source Code Optimization Techniques for Data Flow Dominated Embedded Software. Dresden / Germany [BibTex]

  • Karl-Heinz Zimmermann (2003). A Special Purpose Array Processor Architecture for the Molecular Dynamics Simulation of Point-Mutated Proteins. Journal of Signal Processing Systems. 35. (3), 297-309 [Abstract] [BibTex]

  • Heiko Falk, Peter Marwedel and Francky Catthoor (2003). Control Flow driven Splitting of Loop Nests at the Source Code Level. Kluwer Academic Publishers: [Abstract] [BibTex]

  • Heiko Falk, Cédric Ghez, Miguel Miranda and Rainer Leupers (2003). High-level Control Flow Transformations for Performance Improvement of Address-Dominated Multimedia Applications. In Proceedings of the 11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) Hiroshima / Japan 338-344 [Abstract] [BibTex]

  • Heiko Falk and Peter Marwedel (2003). Control Flow driven Splitting of Loop Nests at the Source Code Level. In Proceedings of Design, Automation and Test in Europe (DATE) Munich / Germany 410-415 [Abstract] [BibTex]

  • Karl-Heinz Zimmermann (2003). An Introduction to Protein Informatics. Kluwer Academic Publishers: [Abstract] [BibTex]

  • Rolf Drechsler and Junhao Shi and Goerschwin Fey (2003). MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits. Great Lakes Symp. VLSI (GLS) 80-83 [BibTex]

  • Goerschwin Fey and Rolf Drechsler (2003). A Hybrid Approach Combining Symbolic and Structural Techniques for Disjoint SOP Minimization. Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 54-60 [BibTex]

  • Goerschwin Fey and Rolf Drechsler (2003). Finding Good Counter-Examples to Aid Design Verification. ACM/IEEE Int'l Conference on Formal Methods and Models for Codesign (MEMOCODE) 51-52 [BibTex]

  • Goerschwin Fey and Sebastian Kinder and Rolf Drechsler (2003). Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques. IEEE Int'l Symposium on Multi-Valued Logic (ISMVL) 361-366 [BibTex]

  • Goerschwin Fey and Junhao Shi and Rolf Drechsler (2003). BDD Circuit Optimization for Path Delay Fault-Testability. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ) [BibTex]

  • Daniel Große and Goerschwin Fey and Rolf Drechsler (2003). Modeling Multi-Valued Circuits in SystemC. IEEE Int'l Symposium on Multi-Valued Logic (ISMVL) 281-286 [BibTex]

  • Junhao Shi and Goerschwin Fey and Rolf Drechsler (2003). BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. Asian Test Symposium (ATS) 290-293 [BibTex]

  • Junhao Shi and Goerschwin Fey and Rolf Drechsler (2003). BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. IEEE European Test Workshop (ETW) 109-110 [BibTex]

  • Junhao Shi and Goerschwin Fey and Rolf Drechsler (2003). Random Pattern Testability of Circuits Derived from BDDs. IEEE Workshop on RTL and High Level Testing (WRTLT) 70-78 [BibTex]

  • Klaus Winkelmann and Hans-Joachim Trylus and Dominik Stoffel and Goerschwin Fey (2003). Cost-efficient Formal Block Verification for ASIC Design. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 184-188 [BibTex]

2002

  • Heiko Falk (2002). Control Flow Optimization by Loop Nest Splitting at the Source Code Level. Dortmund / Germany [Abstract] [BibTex]

  • Karl-Heinz Zimmermann (2002). Efficient DNA sticker algorithms for NP-complete graph problems. Computer Physics Communications. 144. (3), 297-309 [Abstract] [BibTex]

  • Goerschwin Fey and Rolf Drechsler (2002). Minimizing the Number of Paths in BDDs. Int'l Workshop on Boolean Problems (IWSBP) [BibTex]

  • Goerschwin Fey and Rolf Drechsler (2002). Minimizing the Number of Paths in BDDs. Symposium on Integrated Circuits and Systems Design (SBCCI) 359-364 [BibTex]

  • Goerschwin Fey and Rolf Drechsler (2002). Utilizing BDDs for Disjoint SOP Minimization. IEEE Midwest Symposium on Circuits and Systems (MWSCAS) 306-309 [BibTex]

  • Jörg Ritter and Goerschwin Fey and Paul Molitor (2002). SPIHT implemented in a XC4000 device. IEEE Midwest Symposium on Circuits and Systems (MWSCAS) 239-242 [BibTex]

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