Institute of Embedded Systems

2018

• Karl-Heinz Zimmermann (2018). Computations in Stochastic Acceptors. arXiv. [Abstract] [BibTex]
  
  
• Karl-Heinz Zimmermann (2018). Computability Theory. Hamburg University of Technology: [Abstract] [BibTex]
  
  
• Kateryna Muts, Arno Luppold and Heiko Falk (2018). Multi-Objective Optimization for the Compiler of Hard Real-Time Systems. In Proceedings of the 23rd International Symposium on Mathematical Programming (ISMP) Bordeaux / France [Abstract] [BibTex]
  
  
• Kateryna Muts, Arno Luppold and Heiko Falk (2018). Multi-Criteria Compiler-Based Optimization of Hard Real-Time Systems. In Proceedings of the 21st International Workshop on Software & Compilers for Embedded Systems (SCOPES) St. Goar / Germany 54-57 [Abstract] [BibTex]
  
  
• Mikko Roth, Arno Luppold and Heiko Falk (2018). Measuring and Modeling Energy Consumption of Embedded Systems for Optimizing Compilers. In Proceedings of the 21st International Workshop on Software & Compilers for Embedded Systems (SCOPES) St. Goar / Germany 86-89 [Abstract] [BibTex]
  
  
• Karl Janson and Carl Johann Treudler and Thomas Hollstein and Jaan Raik and Maksim Jenihhin and Goerschwin Fey (2018). Software-Level TMR Approach for On-Board Data Processing in Space Applications. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) [BibTex]
  
  
• Jan Malburg and Heinz Riener and Goerschwin Fey (2018). Mining Latency Guarantees for RTL Designs. IEEE Int'l Symposium on Multi-Valued Logic (ISMVL) [BibTex]
  
  

2017

• Karl-Heinz Zimmermann (2017). Computability Theory. Hamburg University of Technology: [Abstract] [BibTex]
  
  
• Heiko Falk (2017). Timing Analysis and Code Optimization for Massively-Parallel Real-Time Systems. Stuttgart / Germany [BibTex]
  
  
• Heiko Falk (2017). Compilation Techniques for Parallel, Safety-Critical Systems with Real-Time Constraints. Seoul / South Korea [BibTex]
  
  
• Dominic Oehlert, Arno Luppold and Heiko Falk (2017). Bus-aware Static Instruction SPM Allocation for Multicore Hard Real-Time Systems. In Proceedings of the 29th Euromicro Conference on Real-Time Systems (ECRTS) Dubrovnik / Croatia 1:1-1:22 [Abstract] [BibTex]
  
  
• Peter Marwedel, Heiko Falk, and Olaf Neugebauer (2017). Memory-Aware Optimization of Embedded Software for Multiple Objectives. Springer: [Abstract] [BibTex]
  
  
• Arno Luppold and Heiko Falk (2017). Schedulability-Aware SPM Allocation for Preemptive Hard Real-Time Systems with Arbitrary Activation Patterns. In Proceedings of Design, Automation and Test in Europe (DATE) Lausanne / Switzerland 1074-1079 [Abstract] [BibTex]
  
  
• Eberle Rambo, Selma Saidi and Rolf Ernst (2017). Designing Networks-on-Chip for High Assurance Real-Time Systems. In Proceedings of the International Symposium on Dependable computing (PRDC) Christchurch / New Zealand [Abstract] [BibTex]
  
  
• Gökçe Aydos and Goerschwin Fey (2017). Empirical Results on Parity-based Soft Error Detection with Software-based Retry. Microprocessors and Microsystems (MICPRO). 62-68 [BibTex]
  
  
• Serhiy Avramenko and Matteo Sonza Reorda and Massimo Violante and Goerschwin Fey (2017). A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms. Journal of Electronic Testing: Theory and Applications (JETTA). 53-64 [BibTex]
  
  
• Tino Flenker and Goerschwin Fey (2017). Mapping Abstract and Concrete Hardware Models for Design Understanding. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) [BibTex]
  
  
• Tino Flenker and Jan Malburg and Görschwin Fey and Serhiy Avramenko and Massimo Violante and Matteo Sonza Reorda (2017). Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects. IEEE Annual Symposium on VLSI (ISVLSI) [BibTex]
  
  
• Jan Malburg and Tino Flenker and Goerschwin Fey (2017). Property Mining using Dynamic Dependency Graphs. ASP Design Automation Conference (ASPDAC) 244-250 [BibTex]
  
  
• Jan Malburg and Heinz Riener and Goerschwin Fey (2017). Mining Latency Guarantees for RT-level Designs. Workshop on Design Automation for Understanding Hardware Designs (DUHDe) [BibTex]
  
  
• Meß, Jan-Gerd and Schmidt, Robert and Fey, Goerschwin (2017). Adaptive Compression Schemes for Housekeeping Data. IEEE Aerospace Conference (AEROCONF) [BibTex]
  
  
• Heinz Riener and Rüdiger Ehlers and Goerschwin Fey (2017). CEGAR-Based EF Synthesis of Boolean Functions with an Application to Circuit Rectification. ASP Design Automation Conference (ASPDAC) 251-256 [BibTex]
  
  
• Heinz Riener and Ruediger Ehlers and Goerschwin Fey (2017). Counterexample-Guided EF Synthesis of Boolean Functions. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) [BibTex]
  
  
• Heinz Riener and Goerschwin Fey (2017). Computing Exact Fault Candidates Incrementally. Workshop on Design Automation for Understanding Hardware Designs (DUHDe) [BibTex]
  
  
• Heinz Riener and Robert Koenighofer and Goerschwin Fey and Roderick Bloem (2017). SMT-Based CPS Parameter Synthesis. Applied Verification for Continuous and Hybrid Systems (ARCH) 126-133 [BibTex]
  
  
• Robert Schmidt and Alberto Garcia-Ortiz and Goerschwin Fey (2017). Temporal Redundancy Latch-based Architecture for Soft Error Mitigation. IEEE International On-Line Testing Symposium (IOLTS) 240-243 [BibTex]
  
  
• Robert Schmidt and Alberto Garcia-Ortiz and Goerschwin Fey (2017). Temporal Redundancy Latch-based Architecture for Soft Error Mitigation. [BibTex]
  
  
• Niels Thole and Goerschwin Fey (2017). Empirical Evaluation of a Formal Conservative Analysis to Prove Robustness under Variability. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ) [BibTex]
  
  

2016

• Jorge Echavaria, Stefan Wildermann, Andreas Becher, Jürgen Teich and Daniel Ziener (2016). FAU: Fast Approximate Adder Units on LUT-Based FPGAs. In Proceedings of the International Conference on Field Programmable Technology (FPT) Xi'an / China [BibTex]
  
  
• Thorbjörn Posewsky and Daniel Ziener (2016). Efficient Deep Neural Network Acceleration through FPGA-based Batch Processing. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) Cancun / Mexico [Abstract] [BibTex]
  
  
• Karl-Heinz Zimmermann (2016). Computability Theory. Hamburg University of Technology: [Abstract] [BibTex]
  
  
• Heiko Falk (2016). Achieving Timing Predictability by Combining Models. Schloss Dagstuhl / Germany [BibTex]
  
  
• Adam Kostrzewa, Sebastian Tobuschat, Selma Saidi and Rolf Ernst (2016). Supporting Suspension-based Locking Mechanisms for Real-Time Networks-on-chips. In Proceedings of the 24th International Conference on Real-Time Networks and Systems (RTNS) Brest / France 215-224 [Abstract] [BibTex]
  
  
• Adam Kostrzewa, Selma Saidi and Rolf Ernst (2016). Multi-Path Scheduling for Multimedia Traffic in Safety Critical On-chip Network. In Proceedings of the 14th ACM/IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia) Pittsburgh / USA 37-46 [Abstract] [BibTex]
  
  
• Adam Kostrzewa, Sebastian Tobuschat, Selma Saidi and Rolf Ernst (2016). Safe and Dynamic Traffic Rate Control for Networks-on-Chips. In Proceedings of the 10th International Symposium on Networks-on-Chip (NOCS) Nara / Japan 1-8 [Abstract] [BibTex]
  
  
• Daniel Ziener, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Schürfeld, Jürgen Teich, Jörg-Stephan Vogt and Helmut Weber (2016). FPGA-Based Dynamically Reconfigurable SQL Query Processing. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 9. (4), 25:1-25:24 [Abstract] [BibTex]
  
  
• Heiko Falk, Sebastian Altmeyer, Peter Hellinckx, Björn Lisper, Wolfgang Puffitsch, Christine Rochange, Martin Schoeberl, Rasmus Bo Sørensen, Peter Wägemann and Simon Wegener (2016). TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research. In Proceedings of the 16th International Workshop on Worst-Case Execution Time Analysis (WCET) Toulouse / France 2:1-2:10 [Abstract] [BibTex]
  
  
• Wolfgang Büter, Dominic Oehlert and Alberto García-Ortiz (2016). ERRCA: A buffer-efficient reconfigurable optical Network-on-Chip with permanent-error recognition. In Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) Tallinn / Estonia 1-6 [Abstract] [BibTex]
  
  
• Heiko Falk (2016). WCET-Aware Compilation and Optimization for Real-Time Systems. Grenoble / France [BibTex]
  
  
• Dirk Koch, Daniel Ziener and Frank Hannig (2016). FPGA versus Software Programming: Why, When, and How?. Springer: [Abstract] [BibTex]
  
  
• Dirk Koch, Frank Hannig and Daniel Ziener (2016). FPGAs for Software Programmers. Springer: [Abstract] [BibTex]
  
  
• Andreas Becher, Jorge Echavaria, Daniel Ziener, Stefan Wildermann and Jürgen Teich (2016). A LUT-Based Approximate Adder. In Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Washington DC / USA [Abstract] [BibTex]
  
  
• Dominic Oehlert, Arno Luppold and Heiko Falk (2016). Practical Challenges of ILP-based SPM Allocation Optimizations. In Proceedings of the 19th International Workshop on Software & Compilers for Embedded Systems (SCOPES) St. Goar / Germany 86-89 [Abstract] [BibTex]
  
  
• Arno Luppold, Christina Kittsteiner and Heiko Falk (2016). Cache-Aware Instruction SPM Allocation for Hard Real-Time Systems. In Proceedings of the 19th International Workshop on Software & Compilers for Embedded Systems (SCOPES) St. Goar / Germany 77-85 [Abstract] [BibTex]
  
  
• Heiko Falk and Arno Luppold (2016). Schedulability-Aware Code Optimization for Multi-Task Real-Time Systems. Paris / France [BibTex]
  
  
• Adam Kostrzewa, Selma Saidi, Leonardo Ecco and Rolf Ernst (2016). Dynamic admission control for real-time networks-on-chips. In Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC) Macao 719-724 [Abstract] [BibTex]
  
  
• Adam Kostrzewa, Selma Saidi and Rolf Ernst (2016). Slack-based resource arbitration for real-time Networks-on-Chip. In Proceedings of Design, Automation and Test in Europe (DATE) Dresden / Germany 1012-1017 [Abstract] [BibTex]
  
  
• Eberle Rambo, Selma Saidi and Rolf Ernst (2016). Providing Formal Latency Guarantees for ARQ-based Protocols in Networks-on-Chip. In Proceedings of Design, Automation and Test in Europe (DATE) Dresden / Germany 103-108 [Abstract] [BibTex]
  
  
• Gadi Aleksandrowicz and Eli Arbel and Roderick Bloem and Timon ter Braak and Sergei Devadze and Goerschwin Fey and Maksim Jenihhin and Artur Jutman and Hans G. Kerkhoff and Robert Könighofer and Jan Malburg and Shiri Moran and Jaan Raik and Gerard Rauwerda and Heinz Riener and Franz Röck and Konstantin Shibin and Kim Sunesen and Jinbo Wan and Yong Zhao (2016). Designing Reliable Cyber-Physical Systems. Forum on Specification and Design Languages (FDL) [BibTex]
  
  
• Gökçe Aydos and Goerschwin Fey (2016). Exploiting Error Detection Latency for Parity-based Soft Error Detection. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) [BibTex]
  
  
• Serhiy Avramenko and Matteo Sonza Reorda and Massimo Violante and Goerschwin Fey and Jan-Gerd Meß and Robert Schmidt (2016). On the robustness of compression algorithms for space applications. IEEE International On-Line Testing Symposium (IOLTS) [BibTex]
  
  
• Serhiy Avramenko and Matteo Sonza Reorda and Massimo Violante and Goerschwin Fey (2016). Analysis of the Effects of Soft Errors on Compression Algorithms Through Fault Injection Inside Program Variables. IEEE Latin-American Test Symposium (LATS) 14-19 [BibTex]
  
  
• Tino Flenker and Goerschwin Fey (2016). Matching Abstract and Concrete Hardware Models for Design Understanding. Workshop on Design Automation for Understanding Hardware Designs (DUHDe) [BibTex]
  
  
• Ian Harris and Sandip Ray and Goerschwin Fey and Mathias Soeken (2016). Multilevel Design Understanding: From Specification to Logic. IEEE/ACM Int'l Conf. on CAD (ICCAD) [BibTex]
  
  
• Goerschwin Fey and Jaan Raik (Organizers) (2016). Designing Reliable Cyber-Physical Systems. [BibTex]
  
  
• Ian Harris and Sandip Ray and Goerschwin Fey and Mathias Soeken (2016). Multilevel Design Understanding: From Specification to Logic (Special Session). [BibTex]
  
  
• Niklas Krafczyk and Heinz Riener and Goerschwin Fey (2016). WCET Overapproximation for Software in the Context of a Cyber-Physical System. IEEE/IFIP Int'l Conference on VLSI and System-on-Chip (VLSI-SoC) [BibTex]
  
  
• Jan Malburg and Alexander Finder and Goerschwin Fey (2016). Debugging hardware designs using dynamic dependency graphs. Microprocessors and Microsystems (MICPRO). 347-359 [BibTex]
  
  
• Jan Malburg and Tino Flenker and Goerschwin Fey (2016). Generating Good Properties from a Small Number of Use Cases. International Verification and Security Workshop (IVSW) [BibTex]
  
  
• Jan-Gerd Meß and Robert Schmidt and Goerschwin Fey and Frank Dannemann (2016). On the Compression of Spacecraft Housekeeping Data using Discrete Cosine Transforms. ESA International Tracking, Telemetry and Command Systems for Space Applications (TTC) [BibTex]
  
  
• Heinz Riener and Goerschwin Fey (2016). Exact Diagnosis using Boolean Satisfiability. IEEE/ACM Int'l Conf. on CAD (ICCAD) 53:1-53:8 [BibTex]
  
  
• Heinz Riener and Goerschwin Fey (2016). Counterexample-Guided Diagnosis. International Verification and Security Workshop (IVSW) [BibTex]
  
  
• Heinz Riener and Finn Haedicke and Stefan Frehse and Mathias Soeken and Daniel Große and Rolf Drechsler and Goerschwin Fey (2016). metaSMT: Focus On Your Application And Not On Solver Integration. International Journal on Software Tools for Technology Transfer (STTT). 1-17 [BibTex]
  
  
• Niels Thole and Lorena Anghel and Goerschwin Fey (2016). A Hybrid Algorithm to Conservatively Check the Robustness of Circuits (extended abstract). IEEE European Test Symposium (ETS) 2 [BibTex]
  
  
• Niels Thole and Lorena Anghel and Goerschwin Fey (2016). A Hybrid Algorithm to Conservatively Check the Robustness of Circuits. IEEE Annual Symposium on VLSI (ISVLSI) 278-283 [BibTex]
  
  
• Niels Thole and Lorena Anghel and Goerschwin Fey (2016). A Hybrid Algorithm to Conservatively Check the Robustness of Circuits. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ) [BibTex]
  
  
• Niels Thole and Heinz Riener and Goerschwin Fey (2016). Equivalence Checking on ESL Utilizing A Priori Knowledge. Forum on Specification and Design Languages (FDL) [BibTex]
  
  
• Sallam Abualhaija, Karl-Heinz Zimmermann (2016). D-Bees: A novel method inspired by bee colony optimization for solving word sense disambiguation. Swarm and Evolutionary Computation. 27. 188-195 [BibTex]
  
  

2015

• Andreas Becher, Daniel Ziener, Klaus Meyer-Wegener and Jürgen Teich (2015). A Co-Design Approach for Accelerated SQL Query Processing via FPGA-based Data Filtering. In Proceedings of the International Conference on Field-Programmable Technology (FPT) Queenstown / New Zealand [Abstract] [BibTex]
  
  
• Andreas Becher, Jorge Echavarria, Daniel Ziener and Jürgen Teich (2015). Approximate Adder Structures on FPGAs. In Proceedings of the Workshop on Approximate Computing (AC) Paderborn / Germany [Abstract] [BibTex]
  
  
• Karl-Heinz Zimmermann (2015). Computability Theory. Hamburg University of Technology: [Abstract] [BibTex]
  
  
• Arno Luppold and Heiko Falk (2015). Schedulability aware WCET-Optimization of Periodic Preemptive Hard Real-Time Multitasking Systems. In Proceedings of the 18th International Workshop on Software & Compilers for Embedded Systems (SCOPES) St. Goar / Germany 101-104 [Abstract] [BibTex]
  
  
• Arno Luppold and Heiko Falk (2015). Code Optimization of Periodic Preemptive Hard Real-Time Multitasking Systems. In Proceedings of the 18th International Symposium on Real-Time Distributed Computing (ISORC) Auckland / New Zealand 35-42 [Abstract] [BibTex]
  
  
• Che-Wei Chang, Jian-Jia Chen, Tei-Wei Kuo and Heiko Falk (2015). Real-Time Task Scheduling on Island-Based Multi-Core Platforms. IEEE Transactions on Parallel and Distributed Systems (TPDS). 26. (2), 538-550 [Abstract] [BibTex]
  
  
• Gökçe Aydos and Goerschwin Fey (2015). Empirical Results on Parity-based Soft Error Detection with Software-based Retry. IEEE Nordic Circuits and Systems Conference (NORCAS) [BibTex]
  
  
• Mehdi Dehbashi and Goerschwin Fey (2015). Debug Automation from Pre-Silicon to Post-Silicon. [BibTex]
  
  
• Mehdi Dehbashi and Goerschwin Fey (2015). Transaction-based online debug for NoC-based multiprocessor SoCs. Microprocessors and Microsystems (MICPRO). 157-166 [BibTex]
  
  
• Emmanuelle Encrenaz-Tiphene and Goerschwin Fey (Organizers) (2015). Workshop on Design Automation for Understanding Hardware Designs (DUHDe). [BibTex]
  
  
• Tino Flenker and André Sülflow and Goerschwin Fey (2015). Diagnostic Tests and Diagnosis for Delay Faults using Path Segmentation. Asian Test Symposium (ATS) 145-150 [BibTex]
  
  
• Jabier Martinez and Jan Malburg and Tewfik Ziadi and Goerschwin Fey (2015). Towards analysing feature locations through testing traces with BUT4Reuse. Workshop on Design Automation for Understanding Hardware Designs (DUHDe) 10-15 [BibTex]
  
  
• Heinz Riener and Rüdiger Ehlers and Goerschwin Fey (2015). Path-Based Program Repair. International Workshop on Formal Engineering approaches to Software Components and Architectures (FESCA), Satellite event of ETAPS 22-32 [BibTex]
  
  
• Heinz Riener and Michael Kirkedal Thomsen and Goerschwin Fey (2015). Execution Tracing of C Code for Formal Analysis (Extended Abstract). ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 160-164 [BibTex]
  
  
• Niels Thole and Goerschwin Fey and Alberto Garcia-Ortiz (2015). Conservatively Analyzing Transient Faults. IEEE Annual Symposium on VLSI (ISVLSI) 50-55 [BibTex]
  
  
• Niels Thole and Goerschwin Fey and Alberto Garcia-Ortiz (2015). Analyzing an SET at Gate Level using a Conservative Approach. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ) [BibTex]
  
  
• Niels Thole and Heinz Riener and Fey, Goerschwin (2015). Equivalence Checking on System Level using A Priori Knowledge. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) 177-182 [BibTex]
  
  
• Trond Ytterdal and Snorre Aunet and General Chairs and Bjørn B. Larsen and Görschwin Fey (editors) (2015). 22nd European conference on circuit theory and design, ECCTD 2015, Trondheim, Norway, August 24-26, 2015. [BibTex]
  
  

2014

• Arno Luppold and Heiko Falk (2014). Schedulability-Oriented WCET-Optimization of Hard Real-Time Multitasking Systems. In Proceedings of the 8th Junior Researcher Workshop on Real-Time Computing (JRWRTC) Versailles / France 9-12 [Abstract] [BibTex]
  
  
• Heiko Falk (Ed.) (2014). Proceedings of the 14th International Workshop on Worst-Case Execution Time Analysis (WCET). Madrid / Spain [www] [BibTex]
  
  
• Heiko Falk (2014). WCET-aware compilation and optimization. Venice / Italy [BibTex]
  
  
• Emmanuelle Encrenaz-Tiphene and Goerschwin Fey (Organizers) (2014). Workshop on Design Automation for Understanding Hardware Designs (DUHDe). [BibTex]
  
  
• Alexander Finder and André Sülflow and Goerschwin Fey (2014). Latency Analysis for Sequential Circuits. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 643-647 [BibTex]
  
  
• Goerschwin Fey (2014). Command and Data Handling Infrastructure for Space Systems (Invited Talk). IEEE Int'l Symposium on Multi-Valued Logic (ISMVL) [BibTex]
  
  
• Daniel Lüdtke and Karsten Westerdorff and Kai Stohlmann and Anko Börner and Olaf Maibaum and Ting Peng and Benjamin Weps and Goerschwin Fey and Andreas Gerndt (2014). OBC-NG: Towards a Reconfigurable On-board Computing Architecture for Spacecraft. IEEE Aerospace Conference (AEROCONF) [BibTex]
  
  
• Jan Malburg and Emmanuelle Encrenaz-Tiphene and Goerschwin Fey (2014). Mutation based Feature Localization. International Workshop on Microprocessor Test and Verification (MTV) 49-54 [BibTex]
  
  
• Jan Malburg and Emmanuelle Encrenaz-Tiphene and Goerschwin Fey (2014). Mutation based Feature Localization. Workshop on Design Automation for Understanding Hardware Designs (DUHDe) [BibTex]
  
  
• Jan Malburg and Alexander Finder and Goerschwin Fey (2014). A Simulation Based Approach for Automated Feature Localization. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 1886-1899 [BibTex]
  
  
• Jan Malburg and Niklas Krafczyk and Goerschwin Fey (2014). Automatically Connecting Hardware Blocks via Light-Weight Matching Techniques. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) [BibTex]
  
  
• Heinz Riener and Oliver Keszocze and Rolf Drechsler and Goerschwin Fey (2014). A Logic for Cardinality Constraints (Extended Abstract). ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 217-220 [BibTex]
  
  
• Heinz Riener and Mathias Soeken and Clemens Werther and Goerschwin Fey and Rolf Drechsler (2014). metaSMT: A Unified Interface to SMT-LIB2. Forum on Specification and Design Languages (FDL) [BibTex]
  
  
• Carl Johann Treudler and Jan-Carsten Schröder and Fabian Greif and Kai Stohlmann and Gökçe Aydos and Goerschwin Fey (2014). Scalability of a Base Level Design for an On-Board-Computer for Scientific Missions. Data Systems In Aerospace (DASIA) [BibTex]