Embedded safety-critical systems, such as automotive and avionics systems, are moving from single-core architectures to multi-cores in order to enable new features in terms of performance, safety and security. Multi-core architectures are well established in general-purpose computing and application-specific domains like, e.g., high-performance computing. However, embedded systems have strict requirements in terms of timing and safety, and standard multi-core platforms are not designed to meet these requirements. Indeed, standard commercial off-the-shelf (COTS) multi-core components are optimized to improve the average-case performance and not the worst case - the use of cached memories is the best example of such a feature. Furthermore, shared hardware resources impose a strong timing correlation between concurrently running software functions in the same chip. This introduces additional non-functional dependencies that may induce unpredictable overloads possibly violating the timing constraints of a system.

Therefore, the use of multi-cores in real-time and safety-critical systems is becoming an active area of research to provide powerful design, analysis, and optimization techniques required to ensure both the predictability and efficiency of such platforms.

In this context, this seminar's topics include:

• Worst-case execution time analysis for multi-core processors
• Design of predictable multi-core platforms
• Multi-core ECUs for future cars (AUTOSAR)
• Opportunities for FPGAs in Automatic Driving Assistance Systems
• Use of multi-cores in avionics systems
• Predictable allocation of shared resources in multi-core systems
• Real-Time Operating Systems for safety-critical multi-core platforms
• Certification of real-time multi-core platforms