Rechnerarchitektur / Computer Architecture
Competences
This module presents advanced concepts from the discipline of computer architecture. In the beginning, a broad overview over various programming models is given, both for general-purpose computers (e.g., the MIPS architecture) and for special-purpose machines (e.g., signal processors). Next, foundational aspects of the micro-architecture of processors are covered. Here, the focus particularly lies on the so-called pipelining and the methods used for the acceleration of instruction execution used in this context. In the last section, computer systems with more than one processor or several functional units are discussed.
The students are able to describe the organization of processors. They know the different architectural principles and programming models. The students examine various structures of the MIPS architecture and are able to explain and to analyze pipeline conflicts. They evaluate different structures of memory hierarchies, know parallel computer architectures and are able to distinguish between instruction- and data-level parallelism.
Contents
- Chapter 1: Introduction
- Chapter 2: Basics of VHDL
- Chapter 3: Instruction Set Architectures
- Chapter 4: Realization of basic data types
- Chapter 5: Dynamic Scheduling
- Chapter 6: Branch Prediction
- Chapter 7: Superscalar Architectures
- Chapter 8: Memory Hierarchies
In the practical labs, the students will learn how to specify hardware components using the hardware description language VHDL. They will realize their very own hardware components, raising from controllers of simple LEDs or displays up to a lightweight MIPS-style processor using reconfigurable FPGAs.
Bibliography
- John L. Hennessy, David A. Patterson. Computer Architecture - A Quantitative Approach. 5th Edition, Morgan Kaufmann, 2012.
- Andrew S. Tanenbaum, James R. Goodman. Computerarchitektur - Strukturen, Konzepte, Grundlagen. 4th Edition, Pearson Studium, 2004.
Requirements
- Course "Technische Informatik / Computer Engineering" (mandatory)