Timing Analysis on Code-Level (TACLe)
Fact Sheet
Acronym | TACLe |
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Name | Timing Analysis on Code-Level |
Homepage | www.tacle.eu |
Role of TUHH | Action Vice Chair, member of Working Groups 1, 2 and 4 |
Start Date | 07/11/2012 |
End Date | 06/11/2016 |
Funds Donor | COST Office Brussels |
Summary
TACLe is a four years lasting COST Action funded by the COST Office in Brussels.
Many embedded systems are safety-critical real-time systems that must process data within given deadlines. To validate real-time properties, timing analyses of program code are mandatory. Research on techniques for timing analysis of software touches many areas within computer science, e.g., computer architecture, compiler construction and formal verification.
This COST Action aims to cross-link the leading European researchers in these areas and thus to strengthen Europe's leading position in the field of timing analysis. TACLe's research activities include timing models for multicore systems, support of timing analysis by software development tools, early-stage timing analysis right in the beginning of the software development cycle, and the consideration of resources other than time like, e.g., energy dissipation.
TACLe Publications of the Embedded Systems Design Group
[176884] |
Title: Real-Time Task Scheduling on Island-Based Multi-Core Platforms. |
Written by: Che-Wei Chang, Jian-Jia Chen, Tei-Wei Kuo and Heiko Falk |
in: <em>IEEE Transactions on Parallel and Distributed Systems (TPDS)</em>. February (2015). |
Volume: <strong>26</strong>. Number: (2), |
on pages: 538-550 |
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ISBN: 10.1109/TPDS.2013.2297308 |
how published: 15-90 CCK+15 TPDS |
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Note: hfalk, ESD, emp2, tacle
Abstract: With the increasing number of cores in a computing system, how to coordinate the computing units and heterogeneous memory resources has soon become extremely critical for real-time systems. This paper explores the joint considerations of memory management and real-time task scheduling over island-based multi-core architecture, where the local memory module of an island offers shorter access time than the global memory module does. The objective of this work is to minimize the number of needed islands to successfully schedule real-time tasks. When the required amount of the local memory space is specified for each task, a scheduling algorithm is proposed to provide an asymptotic 29/9-approximation bound. When there is flexibility in determining the needed local memory space for each task, we propose an algorithm with an asymptotic 4-approximation bound to jointly manage memory resources and allocate computing cores. In addition to the worst-case approximation analysis, the proposed algorithms are also evaluated with 82 real-life benchmarks with the support of a worst-case execution time analyzer. Moreover, extensive evaluations are conducted to show the capability of the proposed approaches when being used with various computing cores and memory resources.