2014

• Kai Borchers and Goerschwin Fey and Daniel Luedtke (2014). Automatic Performance Tracking of a SpaceWire Network. International SpaceWire Conference
  
  
• Mehdi Dehbashi and Goerschwin Fey (2014). Debug Automation for Synchronization Bugs at RTL. VLSI Design Conference 44-49
  
  
• Mehdi Dehbashi and Goerschwin Fey (2014). Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs. Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP) 400-404
  
  
• Mehdi Dehbashi and Goerschwin Fey (2014). SAT-Based Speedpath Debugging Using Waveforms. IEEE European Test Symposium (ETS) 63-68
  
  
• Mehdi Dehbashi and Goerschwin Fey (2014). Debug Automatisierung für logische Schaltungen unter Zeitvariation mittels Waveforms. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)
  
  
• Emmanuelle Encrenaz-Tiphene and Goerschwin Fey (Organizers) (2014). Workshop on Design Automation for Understanding Hardware Designs (DUHDe).
  
  
• Stephan Eggersglüß and Goerschwin Fey and Ilia Polian (2014). Test digitaler Schaltkreise.
  
  
• Alexander Finder and André Sülflow and Goerschwin Fey (2014). Latency Analysis for Sequential Circuits. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 643-647
  
  
• Goerschwin Fey (2014). Command and Data Handling Infrastructure for Space Systems (Invited Talk). IEEE Int'l Symposium on Multi-Valued Logic (ISMVL)
  
  
• Daniel Lüdtke and Karsten Westerdorff and Kai Stohlmann and Anko Börner and Olaf Maibaum and Ting Peng and Benjamin Weps and Goerschwin Fey and Andreas Gerndt (2014). OBC-NG: Towards a Reconfigurable On-board Computing Architecture for Spacecraft. IEEE Aerospace Conference (AEROCONF)
  
  
• Jan Malburg and Emmanuelle Encrenaz-Tiphene and Goerschwin Fey (2014). Mutation based Feature Localization. International Workshop on Microprocessor Test and Verification (MTV) 49-54
  
  
• Jan Malburg and Emmanuelle Encrenaz-Tiphene and Goerschwin Fey (2014). Mutation based Feature Localization. Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
  
  
• Jan Malburg and Alexander Finder and Goerschwin Fey (2014). A Simulation Based Approach for Automated Feature Localization. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 1886-1899
  
  
• Jan Malburg and Niklas Krafczyk and Goerschwin Fey (2014). Automatically Connecting Hardware Blocks via Light-Weight Matching Techniques. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
  
  
• Heinz Riener and Oliver Keszocze and Rolf Drechsler and Goerschwin Fey (2014). A Logic for Cardinality Constraints (Extended Abstract). ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 217-220
  
  
• Heinz Riener and Mathias Soeken and Clemens Werther and Goerschwin Fey and Rolf Drechsler (2014). metaSMT: A Unified Interface to SMT-LIB2. Forum on Specification and Design Languages (FDL)
  
  
• Niels Thole and Goerschwin Fey (2014). Equivalence Checking on System Level using Stepwise Induction. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 197-200
  
  
• Carl Johann Treudler and Jan-Carsten Schröder and Fabian Greif and Kai Stohlmann and Gökçe Aydos and Goerschwin Fey (2014). Scalability of a Base Level Design for an On-Board-Computer for Scientific Missions. Data Systems In Aerospace (DASIA)
  
  

2013

• Rob Aitken and Goerschwin Fey and Zbigniew T. Kalbarczyk and Frank Reichenbach and Matteo Sonza Reorda (2013). Reliability Analysis Reloaded: How Will We Survive?. Design, Automation and Test in Europe (DATE) 358-367
  
  
• Mehdi Dehbashi and Goerschwin Fey (2013). Debug Automation for Logic Circuits Under Timing Variations. IEEE Design and Test of Computers (DT). 60-69
  
  
• Mehdi Dehbashi and Goerschwin Fey (2013). Efficient Automated Speedpath Debugging. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) 48-53
  
  
• Mehdi Dehbashi and Goerschwin Fey (2013). Towards Debug Automation for Timing Bugs at RTL. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)
  
  
• Mehdi Dehbashi and André Sülflow and Goerschwin Fey (2013). Automated Design Debugging in a Testbench-Based Verification Environment. Microprocessors and Microsystems (MICPRO). 206-217
  
  
• Goerschwin Fey and Matteo Sonza Reorda (Organizers) (2013). Reliability Analysis Reloaded: How Will We Survive? (Embedded Tutorial).
  
  
• Alexander Finder and Jan-Philipp Witte and Goerschwin Fey (2013). Debugging HDL Designs Based on Functional Equivalences with High-Level Specifications. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) 60-65
  
  
• Daniel Grosse and Goerschwin Fey and Rolf Drechsler (2013). Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis. Electronic Communications of the EASST. 13 pages
  
  
• Jan Malburg and Alexander Finder and Goerschwin Fey (2013). Tuning Dynamic Data Flow Analysis to Support Design Understanding. Design, Automation and Test in Europe (DATE) 1179-1184
  
  
• Jan Malburg and Alexander Finder and Goerschwin Fey (2013). Analyse dynamischer Abhängigkeitsgraphen zum Debugging von Hardwaredesigns. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) 59-66
  
  
• Heinz Riener and Goerschwin Fey (2013). Yet a Better Error Explanation Algorithm (Extended Abstract). ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 193-194
  
  
• Heinz Riener and Stefan Frehse and Goerschwin Fey (2013). Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis. Design, Automation and Test in Europe (DATE) 939-942
  
  
• Lukáŝ Sekanina and Görschwin Fey and Jaan Raik and Snorre Aunet and Richard Ruzicka (editors) (2013). 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013.
  
  

2012

• Roderick Bloem and Rolf Drechsler and Goerschwin Fey and Alexander Finder and Georg Hofferek and Robert Könighofer and Jaan Raik and Urmas Repinski and André Sülflow (2012). FoREnSiC - An Automatic Debugging Environment for C Programs. IBM Haifa Verification Conference (HVC) 260-265
  
  
• Mehdi Dehbashi and Goerschwin Fey (2012). Automated Debugging from Pre-Silicon to Post-Silicon. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) 324-329
  
  
• Mehdi Dehbashi and Goerschwin Fey (2012). Automated Post-Silicon Debugging of Failing Speedpaths. Asian Test Symposium (ATS) 13-18
  
  
• Mehdi Dehbashi and Goerschwin Fey (2012). Application of Timing Variation Modeling to Speedpath Diagnosis. System, Software, SoC and Silcon Debug Conference (S4D) 34-37
  
  
• Mehdi Dehbashi and Goerschwin Fey (2012). Automated Debugging from Pre-Silicon to Post-Silicon. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)
  
  
• Mehdi Dehbashi and Goerschwin Fey and Kaushik Roy and Anand Raghunathan (2012). Functional Analysis of Circuits Under Timing Variations. IEEE European Test Symposium (ETS) 177
  
  
• Mehdi Dehbashi and Goerschwin Fey and Kaushik Roy and Anand Raghunathan (2012). Functional Analysis of Circuits Under Timing Variations. edaWorkshop 45-50
  
  
• Mehdi Dehbashi and Goerschwin Fey and Kaushik Roy and Anand Raghunathan (2012). On Modeling and Evaluation of Logic Circuits Under Timing Variations. EUROMICRO Symposium on Digital System Design (DSD) 431-436
  
  
• Finder, Alexander and Fey, Görschwin (2012). Evaluating Debugging Algorithms from a Qualitative Perspective. System Specification and Design Languages - Selected Contributions from FDL 2010 21-36
  
  
• Stefan Frehse and Goerschwin Fey and Eli Arbel and Karen Yorav and Rolf Drechsler (2012). Complete and Effective Robustness Checking by Means of Interpolation. Formal Methods in Computer-Aided Design (FMCAD) 82-90
  
  
• Goerschwin Fey and Masahiro Fujita and Natasha Miskov-Zivanov and Kaushik Roy and Matteo Sonza Reorda (editors) (2012). Verifying Reliability (Dagstuhl Seminar 12341). Dagstuhl Reports. 57-73
  
  
• Goerschwin Fey and Masahiro Fujita and Natasha Miskov-Zivanov and Kaushik Roy and Matteo Sonza Reorda (Organizers) (2012). Verifying Reliability (Dagstuhl Seminar 12341). Dagstuhl Reports.
  
  
• Stefan Frehse and Heinz Riener and Goerschwin Fey (2012). Hardware-Software-Co-Synthese zur Verbesserung der Fehlertoleranz. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) 90-96
  
  
• Goerschwin Fey (2012). Assessing System Vulnerability using Formal Verification Techniques. Annual Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS) - Revised Selected Papers 47-56
  
  
• Jan Malburg and Alexander Finder and Goerschwin Fey (2012). Automated Feature Localization for Hardware Designs using Coverage Metrics. Design Automation Conference (DAC) 941-946
  
  
• Jan Malburg and Alexander Finder and Goerschwin Fey (2012). Automated Feature Localization for Hardware Designs using Coverage Metrics. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
  
  
• Heinz Riener and Goerschwin Fey (2012). Model-Based Diagnosis versus Error Explanation. ACM/IEEE Int'l Conference on Formal Methods and Models for Codesign (MEMOCODE) 43-52
  
  
• Heinz Riener and Goerschwin Fey (2012). FAUST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation. International SPIN Workshop on Model Checking of Software (SPIN) 234-240
  
  
• Heinz Riener and Goerschwin Fey (2012). Model-Based Diagnosis versus Error Explanation. International Workshop on System Level-Design of Automotive Electronics/Software (SLDAES)
  
  
• Jaan Raik (Organizer) (2012). Panel: Can RTL test techniques be applied to software?.
  
  
• Mathias Soeken and Heinz Riener and Robert Wille and Goerschwin Fey and Rolf Drechsler (2012). Verification of Embedded Systems Using Modeling and Implementation Languages. International Workshop on Metamodelling and Code Generation for Embedded Systems (MeCoEs) 67-72
  
  

2011

• Mehdi Dehbashi and Goerschwin Fey (2011). Automated Post-Silicon Debugging of Design Bugs. System, Software, SoC and Silcon Debug Conference (S4D) 67-71
  
  
• Mehdi Dehbashi and André Sülflow and Goerschwin Fey (2011). Automated Design Debugging in a Testbench-Based Verification Environment. EUROMICRO Symposium on Digital System Design (DSD) 479-486
  
  
• Stefan Frehse and Finn Haedicke and Melanie Diepenbeck and Goerschwin Fey and Rolf Drechsler (2011). Hochoptimierter Ablauf zur Robustheitsprüfung. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) 35-42
  
  
• Alexander Finder and André Sülflow and Goerschwin Fey (2011). Latency Analysis for Sequential Circuits. IEEE European Test Symposium (ETS) 129-134
  
  
• Alexander Finder and André Sülflow and Goerschwin Fey (2011). Latency Analysis for Sequential Circuits. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ) 119-124
  
  
• Goerschwin Fey and André Sülflow and Stefan Frehse and Rolf Drechsler (2011). Effective Robustness Analysis using Bounded Model Checking Techniques. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 1239-1252
  
  
• Goerschwin Fey (2011). Orchestrated Multi-Level Information Flow Analysis to Understand SoCs. Design Automation Conference (DAC) 284-285
  
  
• Goerschwin Fey (2011). Assessing System Vulnerability using Formal Verification Techniques. Annual Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS)
  
  
• Daniel Große and Goerschwin Fey and Rolf Drechsler (2011). Enhanced Formal Verification Flow for Circuits Integrating Debugging. Design and Test Technology for Dependable Systems-on-Chip 119-129
  
  
• Finn Haedicke and Stefan Frehse and Goerschwin Fey and Daniel Große and Rolf Drechsler (2011). metaSMT: Focus on Your Application not on Solver Integration. Int'l Workshop on Design and Implementation of Formal Tools and Systems (DIFTS) 22-29
  
  
• Heinz Riener and Roderick Bloem and Goerschwin Fey (2011). Test Case Generation from Mutants using Model Checking Techniques. Mutation 388-397
  
  
• Mathias Soeken and Ulrich Kühne and Martin Freibothe and Goerschwin Fey and Rolf Drechsler (2011). Towards Automatic Property Generation for the Formal Verification of Bus Bridges. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) 417-422
  
  
• Mathias Soeken and Ulrich Kühne and Martin Freibothe and Goerschwin Fey and Rolf Drechsler (2011). Towards Automatic Property Generation for the Formal Verification of Bus Bridges. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
  
  

2010

• Rolf Drechsler and Goerschwin Fey (2010). Formal verification meets robustness checking - techniques and challenges (Tutorial).
  
  
• Stephan Eggersglüß and Goerschwin Fey and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel and Rolf Drechsler (2010). MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. Journal of Electronic Testing: Theory and Applications (JETTA). 307-322
  
  
• Stefan Frehse and Goerschwin Fey (2010). Kompositionelle Formale Robustheitsprüfung. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) 73-74
  
  
• Alexander Finder and Goerschwin Fey (2010). Evaluating Debugging Algorithms from a Qualitative Perspective. Forum on Specification and Design Languages (FDL)
  
  
• Alexander Finder and Goerschwin Fey (2010). Evaluating Debugging Algorithms from a Qualitative Perspective. Int'l Workshop on Boolean Problems (IWSBP)
  
  
• Stefan Frehse and Goerschwin Fey and Rolf Drechsler (2010). A Better-Than-Worst-Case Robustness Measure. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) 78-83
  
  
• Stefan Frehse and Goerschwin Fey and Rolf Drechsler (2010). A Better-Than-Worst-Case Robustness Measure. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ) 19-24
  
  
• Stefan Frehse and Goerschwin Fey and Rolf Drechsler (2010). A Better-Than-Worst-Case Robustness Measure. Int'l Test Conference (ITC)
  
  
• Stefan Frehse and Goerschwin Fey and André Sülflow and Rolf Drechsler (2010). RobuCheck: A Robustness Checker for Digital Circuits. EUROMICRO Symposium on Digital System Design (DSD) 226-231
  
  
• Stefan Frehse and Goerschwin Fey and André Sülflow and Rolf Drechsler (2010). RobuCheck: A Robustness Checker for Digital Circuits. Workshop on Dynamic Aspects in Dependability Model for Fault-Tolerant Systems (DYADEM-FTS) 37-38
  
  
• Goerschwin Fey and André Sülflow and Rolf Drechsler (2010). Towards Unifying Localization and Explanation for Automated Debugging. International Workshop on Microprocessor Test and Verification (MTV) 3-8
  
  
• Goerschwin Fey and André Sülflow and Stefan Frehse and Rolf Drechsler (2010). Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen. it - Information Technology. 216-222
  
  
• Goerschwin Fey (Organizer) (2010). Design Closure for Reliability.
  
  
• Finn Haedicke and Bijan Alizadeh and Goerschwin Fey and Masahiro Fujita and Rolf Drechsler (2010). Polynomial Datapath Optimization using Constraint Solving and Formal Modelling. IEEE/ACM Int'l Conf. on CAD (ICCAD) 756-761
  
  
• André Sülflow and Goerschwin Fey and Rolf Drechsler (2010). Using QBF to Increase Accuracy of SAT-Based Debugging. IEEE Int'l Symposium on Circuits and Systems (ISCAS) 641-644
  
  
• André Sülflow and Goerschwin Fey and Rolf Drechsler (2010). Bounded Fault Tolerance Checking (Invited Talk). Forum on Specification and Design Languages (FDL)
  
  

2009

• Dominique Borrione and Rolf Drechsler and Emmanuelle Encrenaz-Tiphene and Goerschwin Fey (2009). Formal and Semi-formal Methods for Correctness and Robustness (Tutorial).
  
  
• Rolf Drechsler and Stephan Eggersglüß and Goerschwin Fey and Daniel Tille (2009). Test Pattern Generation using Boolean Proof Engines.
  
  
• Rolf Drechsler and Stephan Eggersglüß and Goerschwin Fey and Daniel Tille (2009). Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern. it - Information Technology. 102-111
  
  
• Rolf Drechsler and Stephan Eggersglüß and Goerschwin Fey and Daniel Tille (2009). SAT-based Automatic Test Pattern Generation. Evolutionary Test Generation Dagstuhl-Seminar
  
  
• Rolf Drechsler and Goerschwin Fey (2009). Formale Verifikation und Robustheit (Tutorial).
  
  
• Stefan Frehse and Goerschwin Fey and André Sülflow and Rolf Drechsler (2009). Robustness Check for Multiple Faults using Formal Techniques. EUROMICRO Symposium on Digital System Design (DSD) 85-90
  
  
• Stefan Frehse and Goerschwin Fey and André Sülflow and Rolf Drechsler (2009). Robustness Check for Multiple Faults using Formal Techniques. Workshop on Constraints in Formal Verification (CFV)
  
  
• Goerschwin Fey and André Sülflow and Rolf Drechsler (2009). Computing Bounds for Fault Tolerance using Formal Techniques. Design Automation Conference (DAC) 190-195
  
  
• Goerschwin Fey (2009). Deterministic Algorithms for ATPG under Leakage Constraints. Asian Test Symposium (ATS) 313-316
  
  
• Goerschwin Fey (2009). Algorithms for ATPG under Leakage Constraints. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ) 91-96
  
  
• Toru Nakura and Yutaro Tatemura and Goerschwin Fey and Makoto Ikeda and Satoshi Komatsu and Kunihiro Asada (2009). SAT-Based ATPG Testing of Inter- and Intra-Gate Bridging Faults. European Conference on Circuit Theory and Design (ECCTD) 643-647
  
  
• Frank Rogin and Thomas Klotz and Goerschwin Fey and Rolf Drechsler and Steffen Rülke (2009). Advanced Verification by Automatic Property Generation. IET Computers and Digital Techniques. 338-353
  
  
• André Sülflow and Goerschwin Fey and Cecile Braunstein and Ulrich Kühne and Rolf Drechsler (2009). Increasing the Accuracy of SAT-based Debugging. Design, Automation and Test in Europe (DATE) 1326-1331
  
  
• André Sülflow and Goerschwin Fey and Cecile Braunstein and Ulrich Kühne and Rolf Drechsler (2009). Increasing the Accuracy of SAT-based Debugging. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
  
  
• André Sülflow and Goerschwin Fey and Rolf Drechsler (2009). Using QBF to Increase Accuracy of SAT-based Debugging. Workshop on Constraints in Formal Verification (CFV)
  
  
• André Sülflow and Stefan Frehse and Goerschwin Fey and Rolf Drechsler (2009). Anwendungsbezogene Analyse der Robustheit von digitalen Schaltungen. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) 45-52
  
  
• André Sülflow and Ulrich Kühne and Goerschwin Fey and Daniel Große and Rolf Drechsler (2009). WoLFram - A Word Level Framework for Formal Verification. IEEE/IFIP Int'l Symposium on Rapid System Prototyping (RSP) 11-17
  
  
• André Sülflow and Robert Wille and Goerschwin Fey and Rolf Drechsler (2009). Evaluation of Cardinality Constraints on SMT-based Debugging. IEEE Int'l Symposium on Multi-Valued Logic (ISMVL) 298-303
  
  
• Robert Wille and Goerschwin Fey and Daniel Große and Stephan Eggersglüß and Rolf Drechsler (2009). SWORD: A SAT like prover using word level information. VLSI-SoC: Advanced Topics on Systems on a Chip 175-192