2008

• Rolf Drechsler and Stephan Eggersglüß and Goerschwin Fey and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel and Daniel Tille (2008). On Acceleration of SAT-based ATPG for Industrial Designs. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 1329-1333
  
  
• Goerschwin Fey and Anna Bernasconi and Valentina Ciriani and Rolf Drechsler (2008). On the Construction of Small Fully Testable Circuits with Low Depth. Microprocessors and Microsystems (MICPRO). 263-269
  
  
• Goerschwin Fey and Rolf Drechsler (2008). A Basis for Formal Robustness Checking. Int'l Symposium on Quality Electronic Design (ISQED) 784-789
  
  
• Goerschwin Fey and Rolf Drechsler (2008). Robustness and Usability in Modern Design Flows.
  
  
• Goerschwin Fey and Rolf Drechsler (2008). Synthesis for Detection of Transient Faults. IEICE Workshop on Dependable Computing 161-166
  
  
• Goerschwin Fey and Satoshi Komatsu and Yasuo Furukawa and Masahiro Fujita (2008). Targeting Leakage Constraints during ATPG. Asian Test Symposium (ATS) 225-230
  
  
• Goerschwin Fey and Satoshi Komatsu and Yasuo Furukawa and Masahiro Fujita (2008). Targeting Leakage Constraints during ATPG. IEEE Int'l Workshop on Silicon Debug and Diagnosis (SDD)
  
  
• Goerschwin Fey and Stefan Staber and Roderick Bloem and Rolf Drechsler (2008). Automatic Fault Localization for Property Checking. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 1138-1149
  
  
• Goerschwin Fey and Stefan Staber and Roderick Bloem and Rolf Drechsler (2008). Automatic Fault Localization for Property Checking. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 1138-1149
  
  
• Goerschwin Fey and André Sülflow and Stefan Frehse and Ulrich Kühne and Rolf Drechsler (2008). Formaler Nachweis der Fehlertoleranz von Schaltkreisen. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) 75-82
  
  
• Frank Rogin and Thomas Klotz and Goerschwin Fey and Rolf Drechsler and Steffen Rülke (2008). Automatic Generation of Complex Properties for Hardware Designs. Design, Automation and Test in Europe (DATE) 545-548
  
  
• Frank Rogin and Thomas Klotz and Steffen Rülke and Goerschwin Fey and Rolf Drechsler (2008). Effiziente automatische Generierung von Assertions für industrielle Hardware-Designs. Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
  
  
• André Sülflow and Goerschwin Fey and Roderick Bloem and Rolf Drechsler (2008). Using Unsatisfiable Cores to Debug Multiple Design Errors. Great Lakes Symp. VLSI (GLS) 77-82
  
  
• André Sülflow and Goerschwin Fey and Roderick Bloem and Rolf Drechsler (2008). Debugging Design Errors by Using Unsatisfiable Cores. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 159-168 [doi]
  
  
• André Sülflow and Goerschwin Fey and Rolf Drechsler (2008). Experimental Studies on SMT-based Debugging. IEEE Workshop on RTL and High Level Testing (WRTLT) 93-98
  
  
• André Sülflow and Goerschwin Fey and Stefan Frehse and Ulrich Kühne and Rolf Drechsler (2008). Computing Bounds for Fault Tolerance using Formal Techniques. Workshop on Design for Reliability and Variability (DRV)
  
  
• Robert Wille and Goerschwin Fey and Marc Messing and Gerhard Angst and Lothar Linhard and Rolf Drechsler (2008). Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. EUROMICRO Symposium on Digital System Design (DSD) 542-549
  
  

2007

• Rolf Drechsler and Goerschwin Fey and Sebastian Kinder (2007). An Integrated Approach for Combining BDDs and SAT Provers. Facta Universitatis. 415-436
  
  
• Stephan Eggersglüß and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel (2007). Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. ACM/IEEE Int'l Conference on Formal Methods and Models for Codesign (MEMOCODE) 181-187
  
  
• Stephan Eggersglüß and Goerschwin Fey and Rolf Drechsler (2007). SAT-based ATPG for Path Delay Faults in Sequential Circuits. IEEE Int'l Symposium on Circuits and Systems (ISCAS) 3671-3674
  
  
• Goerschwin Fey and Anna Bernasconi and Valentina Ciriani and Rolf Drechsler (2007). On the Construction of Small Fully Testable Circuits with Low Depth. EUROMICRO Symposium on Digital System Design (DSD) 563-569
  
  
• Goerschwin Fey and Rolf Drechsler (2007). Ein formaler Ansatz zum Robustheitsnachweis. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) 101-108
  
  
• Goerschwin Fey and Rolf Drechsler (2007). Formal Robustness Checking. Workshop on Constraints in Formal Verification (CFV)
  
  
• Goerschwin Fey and Daniel Große and Stephan Eggersglüß and Robert Wille and Rolf Drechsler (2007). Formal Verification on the Word Level using SAT-like Proof Techniques. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
  
  
• Goerschwin Fey and Tim Warode and Rolf Drechsler (2007). Using Structural Learning Techniques in SAT-based ATPG. VLSI Design Conference 69-74
  
  
• Goerschwin Fey (2007). Increasing Robustness and Usability of Circuit Design Tools by Using Formal Techniques. Ausgezeichnete Informatikdissertationen 2006 29-38
  
  
• Daniel Große and Goerschwin Fey and Rolf Drechsler (editors) (2007). SATRIX - Algorithmen für Boolesche Erfüllbarkeit.
  
  
• Sebastian Kinder and Goerschwin Fey and Rolf Drechsler (2007). Estimating the Quality of AND-EXOR Optimization Results. Int'l Workshop on Applications of the Reed-Muller Expansion in Circuit Design
  
  
• André Sülflow and Goerschwin Fey and Rolf Drechsler (2007). Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
  
  
• Stephan Eggersglüß and Daniel Tille and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel (2007). Experimental Studies on SAT-based ATPG for Gate Delay Faults. IEEE Int'l Symposium on Multi-Valued Logic (ISMVL) 6 (6 pages)
  
  
• Daniel Tille and Stephan Eggersglüß and Görschwin Fey and Rolf Drechsler and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel (2007). Studies on Integrating SAT-based ATPG in an Industrial Environment. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)
  
  
• Daniel Tille and Goerschwin Fey and Rolf Drechsler (2007). Instance Generation for SAT-based ATPG. IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS)
  
  
• Robert Wille and Goerschwin Fey and Rolf Drechsler (2007). Building Free Binary Decision Diagrams Using SAT Solvers. Int'l Workshop on Applications of the Reed-Muller Expansion in Circuit Design
  
  
• Robert Wille and Goerschwin Fey and Rolf Drechsler (2007). Building Free Binary Decision Diagrams Using SAT Solvers. Facta Universitatis. 381-394
  
  
• Robert Wille and Goerschwin Fey and Daniel Große and Stephan Eggersglüß and Rolf Drechsler (2007). SWORD: A SAT like prover using word level information. IEEE/IFIP Int'l Conference on VLSI and System-on-Chip (VLSI-SoC) 88-93
  
  

2006

• Rolf Drechsler and Goerschwin Fey (2006). Automatic Test Pattern Generation. School on Formal Methods for Hardware Verification 30-55
  
  
• Rolf Drechsler and Goerschwin Fey and Sebastian Kinder (2006). An Integrated Approach for Combining BDD and SAT Provers. VLSI Design Conference 237-242
  
  
• Goerschwin Fey and Rolf Drechsler (2006). SAT-based Calculation of Source Code Coverage for BMC. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 163-170
  
  
• Goerschwin Fey and Rolf Drechsler (2006). Minimizing the Number of Paths in BDDs - Theory and Algorithm. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 4-11
  
  
• Goerschwin Fey and Daniel Große and Rolf Drechsler (2006). Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks. Design, Automation and Test in Europe (DATE) 1225-1226
  
  
• Goerschwin Fey and Junhao Shi and Rolf Drechsler (2006). Efficiency of multiple-valued encoding in SAT-based ATPG. IEEE Int'l Symposium on Multi-Valued Logic (ISMVL) 25 (6 pages)
  
  
• Goerschwin Fey and Junhao Shi and Rolf Drechsler (2006). Efficiency of multiple-valued encoding in SAT-based ATPG. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ) 107-108
  
  
• Goerschwin Fey and Sean Safarpour and Andreas Veneris and Rolf Drechsler (2006). On the Relation Between Simulation-based and SAT-based Diagnosis. Design, Automation and Test in Europe (DATE) 1139-1144
  
  
• Goerschwin Fey and Tim Warode and Rolf Drechsler (2006). Using Structural Learning Techniques in SAT-based ATPG. Int'l Workshop on Boolean Problems (IWSBP) 63-69
  
  
• Goerschwin Fey (2006). Increasing Robustness and Usability of Circuit Design Tools by Using Formal Techniques.
  
  
• Stefan Staber and Goerschwin Fey and Roderick Bloem and Rolf Drechsler (2006). Automatic Fault Localization for Property Checking. IBM Haifa Verification Conference (HVC) 50-64
  
  

2005

• Andreas Breiter and Goerschwin Fey and Rolf Drechsler (2005). Project-Based Learning in Student Teams in Computer Science Education. Facta Universitatis. 165-180
  
  
• Rolf Drechsler and Goerschwin Fey and Christian Genz and Daniel Große (2005). SyCE: An Integrated Environment for System Design in SystemC. IEEE Int'l Workshop on Rapid System Prototyping (RSP) 258-260
  
  
• Rüdiger Ebendt and Goerschwin Fey and Rolf Drechsler (2005). Advanced BDD Optimization.
  
  
• Goerschwin Fey and Rolf Drechsler (2005). Efficient Hierarchical System Debugging for Property Checking. IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS) 41-46
  
  
• Goerschwin Fey and Rolf Drechsler (editors) (2005). FunTaskIC - Eine integrierte Entwurfsumgebung für SystemC.
  
  
• Sebastian Kinder and Goerschwin Fey and Rolf Drechsler (2005). Controlling the Memory During Manipulation of Word-Level Decision Diagrams. IEEE Int'l Symposium on Multi-Valued Logic (ISMVL) 250-255
  
  
• Junhao Shi and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Juergen Schloeffel and Friedrich Hapke (2005). PASSAT: Efficient SAT-based Test Pattern Generation. IEEE Annual Symposium on VLSI (ISVLSI) 212-217
  
  
• Junhao Shi and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Juergen Schloeffel and Friedrich Hapke (2005). Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits. IEEE Int'l Conference on ASIC (ASICON)
  
  
• Junhao Shi and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Juergen Schloeffel and Friedrich Hapke (2005). PASSAT: Efficient SAT-based Test Pattern Generation. IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS) 166-173
  
  
• Junhao Shi and Goerschwin Fey and Rolf Drechsler (2005). Bridging Fault Testability of BDD Circuits. ASP Design Automation Conference (ASPDAC) 188-191
  
  
• Sean Safarpour and Goerschwin Fey and Andreas Veneris and Rolf Drechsler (2005). Utilizing Don't Care States in SAT-based Bounded Sequential Problems. Great Lakes Symp. VLSI (GLS) 264-269
  
  

2004

• Nicole Drechsler and Mario Hilgemeier and Goerschwin Fey and Rolf Drechsler (2004). Disjoint Sum of Product Minimization by Evolutionary Algorithms. Applications of Evolutionary Computing: EvoWorkshops 198-207
  
  
• Rolf Drechsler and Junhao Shi and Goerschwin Fey (2004). Synthesis of Fully Testable Circuits from BDDs. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 440-443
  
  
• Goerschwin Fey and Rolf Drechsler (2004). Improving Simulation-Based Verification by Means of Formal Methods. ASP Design Automation Conference (ASPDAC) 640-643
  
  
• Goerschwin Fey and Rolf Drechsler (2004). Visualization of Diagnosis Results for Design Debugging. Internatinal Workshop on Post-Binary ULSI Systems (ULSIWS) 1-2
  
  
• Rolf Drechsler and Goerschwin Fey (2004). Design Understanding by Automatic Property Generation. Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 274-281
  
  
• Goerschwin Fey and Rolf Drechsler and Maciej Ciesielski (2004). Algorithms for Taylor Expansion Diagrams. IEEE Int'l Symposium on Multi-Valued Logic (ISMVL) 235-240
  
  
• Goerschwin Fey and Daniel Große and Tim Cassens and Christian Genz and Tim Warode and Rolf Drechsler (2004). ParSyC: An Efficient SystemC Parser. Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 148-154
  
  
• Goerschwin Fey and Junhao Shi and Rolf Drechsler (2004). BDD Circuit Optimization for Path Delay Fault Testability. EUROMICRO Symposium on Digital System Design (DSD) 162-172
  
  
• Klaus Winkelmann and Hans-Joachim Trylus and Dominik Stoffel and Goerschwin Fey (2004). Cost-efficient Block Verification for a UMTS Up-link Chip-rate Coprocessor. Design, Automation and Test in Europe (DATE) 162-167
  
  

2003

• Rolf Drechsler and Junhao Shi and Goerschwin Fey (2003). MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits. Great Lakes Symp. VLSI (GLS) 80-83
  
  
• Goerschwin Fey and Rolf Drechsler (2003). A Hybrid Approach Combining Symbolic and Structural Techniques for Disjoint SOP Minimization. Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 54-60
  
  
• Goerschwin Fey and Rolf Drechsler (2003). Finding Good Counter-Examples to Aid Design Verification. ACM/IEEE Int'l Conference on Formal Methods and Models for Codesign (MEMOCODE) 51-52
  
  
• Goerschwin Fey and Sebastian Kinder and Rolf Drechsler (2003). Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques. IEEE Int'l Symposium on Multi-Valued Logic (ISMVL) 361-366
  
  
• Goerschwin Fey and Junhao Shi and Rolf Drechsler (2003). BDD Circuit Optimization for Path Delay Fault-Testability. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)
  
  
• Daniel Große and Goerschwin Fey and Rolf Drechsler (2003). Modeling Multi-Valued Circuits in SystemC. IEEE Int'l Symposium on Multi-Valued Logic (ISMVL) 281-286
  
  
• Junhao Shi and Goerschwin Fey and Rolf Drechsler (2003). BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. Asian Test Symposium (ATS) 290-293
  
  
• Junhao Shi and Goerschwin Fey and Rolf Drechsler (2003). BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. IEEE European Test Workshop (ETW) 109-110
  
  
• Junhao Shi and Goerschwin Fey and Rolf Drechsler (2003). Random Pattern Testability of Circuits Derived from BDDs. IEEE Workshop on RTL and High Level Testing (WRTLT) 70-78
  
  
• Klaus Winkelmann and Hans-Joachim Trylus and Dominik Stoffel and Goerschwin Fey (2003). Cost-efficient Formal Block Verification for ASIC Design. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 184-188
  
  

2002

• Goerschwin Fey and Rolf Drechsler (2002). Minimizing the Number of Paths in BDDs. Int'l Workshop on Boolean Problems (IWSBP)
  
  
• Goerschwin Fey and Rolf Drechsler (2002). Minimizing the Number of Paths in BDDs. Symposium on Integrated Circuits and Systems Design (SBCCI) 359-364
  
  
• Goerschwin Fey and Rolf Drechsler (2002). Utilizing BDDs for Disjoint SOP Minimization. IEEE Midwest Symposium on Circuits and Systems (MWSCAS) 306-309
  
  
• Jörg Ritter and Goerschwin Fey and Paul Molitor (2002). SPIHT implemented in a XC4000 device. IEEE Midwest Symposium on Circuits and Systems (MWSCAS) 239-242
  
  

2001

• Goerschwin Fey (2001). Set Partitioning in Hierarchical Trees: eine FPGA-Implementierung.